公开(公告)号：US20240393946A1

公开(公告)日：2024-11-28

申请号：US18791933

申请日：2024-08-01

Applicant: KIOXIA CORPORATION

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

公开(公告)号：US20230305704A1

公开(公告)日：2023-09-28

申请号：US18327108

申请日：2023-06-01

Applicant: KIOXIA CORPORATION

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0656 ,  G06F3/0688 ,  G06F3/0659 ,  G06F3/064

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

公开(公告)号：US20220350530A1

公开(公告)日：2022-11-03

申请号：US17684551

申请日：2022-03-02

Applicant: Kioxia Corporation

Inventor： Hideki YOSHIDA ,  Shinichi KANNO ,  Naoki ESAKA

IPC: G06F3/06

Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

公开(公告)号：US20220214966A1

公开(公告)日：2022-07-07

申请号：US17699660

申请日：2022-03-21

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Naoki ESAKA

IPC: G06F12/02 ,  G06F12/0871 ,  G06F13/40 ,  G06F13/16 ,  G06F12/0868

Abstract: According to one embodiment, a controller of a memory system writes write data associated with a set of received write requests to a first write destination storage region in a first write mode of writing a plurality of bits per memory cell, without writing the write data to a second storage region. When receiving from a host a first request to cause a state of the first write destination storage region to transition to a second state in which writing is suspended, the controller transfers un-transferred remaining write data from a write buffer of the host to an internal buffer, and writes the remaining write data to the second storage region in a second write mode of writing 1 bit per memory cell.

公开(公告)号：US20250123756A1

公开(公告)日：2025-04-17

申请号：US18985165

申请日：2024-12-18

Applicant: Kioxia Corporation

Inventor： Koichi NAGAI ,  Naoki ESAKA ,  Toyohide ISSHI

IPC: G06F3/06

Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.

公开(公告)号：US20240427941A1

公开(公告)日：2024-12-26

申请号：US18822835

申请日：2024-09-03

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Yoshiyuki KUDOH

IPC: G06F21/64 ,  G06F21/79

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes storage areas each configured to store user data. The controller acquires first information related to the number of program/erase cycles for at least one of the storage areas. In response to acquisition of the first information, the controller executes a data erase operation on each of the storage areas. In response to completion of the data erase operation, the controller acquires second information related to the number of program/erase cycles for the at least one of the storage areas. The controller generates an erase certificate that includes the first information and the second information.

公开(公告)号：US20240061610A1

公开(公告)日：2024-02-22

申请号：US18499750

申请日：2023-11-01

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA ,  Hiroshi NISHIMURA

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F12/1009 ,  G06F3/064 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

公开(公告)号：US20230076210A1

公开(公告)日：2023-03-09

申请号：US17981817

申请日：2022-11-07

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA ,  Hiroshi NISHIMURA

IPC: G06F3/06 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

公开(公告)号：US20240086099A1

公开(公告)日：2024-03-14

申请号：US18516632

申请日：2023-11-21

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.

公开(公告)号：US20230325112A1

公开(公告)日：2023-10-12

申请号：US18333962

申请日：2023-06-13

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0679 ,  G06F3/0604 ,  G06F12/0804

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.