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公开(公告)号：US20230305752A1
公开(公告)日：2023-09-28
申请号：US18204858
申请日：2023-06-01
Applicant: Kioxia Corporation
Inventor： Neil Buxton , Avadhani Shridhar , Steven Wells , Nicole Ross
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C16/0483 , G06F3/0656 , G11C11/56
Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
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公开(公告)号：US11704061B2
公开(公告)日：2023-07-18
申请号：US17203392
申请日：2021-03-16
Applicant: Kioxia Corporation
Inventor： Neil Buxton , Avadhani Shridhar , Steven Wells , Nicole Ross
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0656 , G06F3/0679 , G11C16/0483 , G11C11/56
Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
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公开(公告)号：US20220350746A1
公开(公告)日：2022-11-03
申请号：US17867074
申请日：2022-07-18
Applicant: Kioxia Corporation
Inventor： Saswati Das , Manish Kadam , Neil Buxton
IPC: G06F12/0866
Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
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公开(公告)号：US11321022B2
公开(公告)日：2022-05-03
申请号：US16731766
申请日：2019-12-31
Applicant: Kioxia Corporation
Inventor： Neil Buxton , Gary James Calder
IPC: G06F3/06 , G06F9/4401
Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.
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公开(公告)号：US20250044971A1
公开(公告)日：2025-02-06
申请号：US18919578
申请日：2024-10-18
Applicant: Kioxia Corporation
Inventor： Neil Buxton , Steven Wells
IPC: G06F3/06
Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including determining superblocks, including first and second superblocks, in a non-volatile memory storage. The non-volatile memory storage includes independent locations that may be planes or dies. The first superblock includes first blocks corresponding to first independent locations, and the second superblock includes second blocks corresponding to second independent locations. A first number of the first independent locations is less than a number of the independent locations. A second number of the second plurality of independent locations is less than the number of the independent locations.
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Patent Agency Ranking
公开(公告)号：US12169641B2
公开(公告)日：2024-12-17
申请号：US18097043
申请日：2023-01-13
Applicant: Kioxia Corporation
Inventor： Avadhani Shridhar , Neil Buxton
IPC: G06F3/06
Abstract: A method for status signaling in a non-volatile memory including a plurality of logical units (LUNs), each of the plurality of LUNs having a status terminal coupled to a common status terminal of the non-volatile memory and a data bus coupled to a common data bus of the non-volatile memory. The method including performing, by a first LUN of the plurality of LUNs, a first set of one or more operations; completing, by the first LUN of the plurality of LUNs, the first set of one or more operations; and sending, by the first LUN via the common terminal, a pulse to a controller responsive to completing the first set of one or more operations.
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17.发明公开公开(公告)号：US20230305745A1
公开(公告)日：2023-09-28
申请号：US17700651
申请日：2022-03-22
Applicant: Kioxia Corporation
Inventor： Nigel Horspool , Steve Wells , Neil Buxton
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/064 , G06F3/0635 , G06F3/0619 , G06F3/0679
Abstract: Various implementations described herein relate to systems, methods, and non-transitory computer-readable media for managing write commands to superblocks, including receiving, by a storage device from a host, a write command and a write data. The write command indicates that the write data is to be written to a first superblock of the storage device. The storage device determines the first superblock lacks sufficient capacity to store the write data. In response to determining that the first superblock lacks the sufficient capacity to store the write data, the storage device programs the write data to at least one of a reserved capacity of the first superblock or a second superblock.
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公开(公告)号：US20230289078A1
公开(公告)日：2023-09-14
申请号：US17690287
申请日：2022-03-09
Applicant: Kioxia Corporation
Inventor： Steven Wells , Neil Buxton , Nigel Horspool , Mohinder Saluja , Paul Suhler
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0659 , G06F3/0604 , G06F3/0673
Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including a non-volatile storage including a superblock and a controller configured to notify a host of a size of the superblock to a host, determine a stream that aligns with the superblock, write data corresponding to the stream to the superblock, and determine that writing the data correspond to the stream has completed.
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公开(公告)号：US12124719B2
公开(公告)日：2024-10-22
申请号：US17577888
申请日：2022-01-18
Applicant: Kioxia Corporation
Inventor： Neil Buxton , Steven Wells
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0634 , G06F3/0659 , G06F3/0679
Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including determining superblocks, including first and second superblocks, in a non-volatile memory storage. The non-volatile memory storage includes independent locations that may be planes or dies. The first superblock includes first blocks corresponding to first independent locations, and the second superblock includes second blocks corresponding to second independent locations. A first number of the first independent locations is less than a number of the independent locations. A second number of the second plurality of independent locations is less than the number of the independent locations.
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公开(公告)号：US12112070B2
公开(公告)日：2024-10-08
申请号：US18204858
申请日：2023-06-01
Applicant: Kioxia Corporation
Inventor： Neil Buxton , Avadhani Shridhar , Steven Wells , Nicole Ross
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0656 , G06F3/0679 , G11C16/0483 , G11C11/56
Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.
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