公开(公告)号：US20110291188A1

公开(公告)日：2011-12-01

申请号：US12787383

申请日：2010-05-25

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7853

摘要： A FinFET is described incorporating at least two fins extending from a common Si containing layer and epitaxial material grown from the common layer and from sidewalls of the fins to introduce strain to the common layer and the fins to increase carrier mobility.

摘要翻译： 描述了FinFET，其包括从共同的含Si层延伸的至少两个翅片和从公共层和翅片的侧壁生长的外延材料，以将应变引入公共层和翅片以增加载流子迁移率。

公开(公告)号：US20110108961A1

公开(公告)日：2011-05-12

申请号：US12614986

申请日：2009-11-09

申请人： KANGGUO CHENG ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： KANGGUO CHENG ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L29/06 ,  H01L21/302

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

摘要翻译： 一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。 结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。 使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

公开(公告)号：US07936017B2

公开(公告)日：2011-05-03

申请号：US12120836

申请日：2008-05-15

申请人： William F. Clark, Jr. ,  Toshiharu Furukawa ,  Xuefeng Hua ,  Charles W. Koburger, III ,  Robert R. Robison

发明人： William F. Clark, Jr. ,  Toshiharu Furukawa ,  Xuefeng Hua ,  Charles W. Koburger, III ,  Robert R. Robison

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78612 ,  H01L29/78621

摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

摘要翻译： 提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。 一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

公开(公告)号：US20090283828A1

公开(公告)日：2009-11-19

申请号：US12120836

申请日：2008-05-15

申请人： William F. Clark, JR. ,  Toshiharu Furukawa ,  Xuefeng Hua ,  Charles W. Koburger, III ,  Robert R. Robison

发明人： William F. Clark, JR. ,  Toshiharu Furukawa ,  Xuefeng Hua ,  Charles W. Koburger, III ,  Robert R. Robison

IPC分类号： H01L29/786 ,  H01L21/425 ,  G06F17/50

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78612 ,  H01L29/78621

摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.

摘要翻译： 提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。 一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

公开(公告)号：US08324036B2

公开(公告)日：2012-12-04

申请号：US12614986

申请日：2009-11-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L21/84

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

摘要翻译： 一种用于制造用于集成电路的特征的方法包括图案化心轴层以包括在集成电路器件的表面上具有至少一个宽度的结构。 结构的暴露的侧壁反应以在侧壁中一体地形成新的化合物，使得新化合物以受控的量延伸到暴露的侧壁中以形成柱。 使用柱作为蚀刻掩模蚀刻柱下方的一个或多个层，以形成用于集成电路器件的特征。

公开(公告)号：US08569868B2

公开(公告)日：2013-10-29

申请号：US13552296

申请日：2012-07-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L29/06

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

摘要翻译： 公开了一种用于半导体器件的结构。 该结构包括第一特征和第二特征。 第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。 第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

公开(公告)号：US20120280365A1

公开(公告)日：2012-11-08

申请号：US13552296

申请日：2012-07-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L29/06

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

摘要翻译： 公开了一种用于半导体器件的结构。 该结构包括第一特征和第二特征。 第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。 第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

公开(公告)号：US08084329B2

公开(公告)日：2011-12-27

申请号：US12693629

申请日：2010-01-26

申请人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

发明人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

摘要翻译： 在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间​​的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。

公开(公告)号：US07470329B2

公开(公告)日：2008-12-30

申请号：US10913323

申请日：2004-08-09

申请人： Gottlieb S. Oehrlein ,  Xuefeng Hua ,  Christian Stolz

发明人： Gottlieb S. Oehrlein ,  Xuefeng Hua ,  Christian Stolz

IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： H01J37/32623

摘要： A plasma processing system includes a source of plasma, a substrate and a shutter positioned in close proximity to the substrate. The substrate/shutter relative disposition is changed for precise control of substrate/plasma interaction. This way, the substrate interacts only with a fully established, stable plasma for short times required for nanoscale processing of materials. The shutter includes an opening of a predetermined width, and preferably is patterned to form an array of slits with dimensions that are smaller than the Debye screening length. This enables control of the substrate/plasma interaction time while avoiding the ion bombardment of the substrate in an undesirable fashion. The relative disposition between the shutter and the substrate can be made either by moving the shutter or by moving the substrate.

摘要翻译： 等离子体处理系统包括等离子体源，基板和靠近基板定位的快门。 为了精确控制衬底/等离子体相互作用，改变衬底/快门相对配置。 这样，衬底仅与材料的纳米级处理所需的短时间内完全建立稳定的等离子体相互作用。 快门包括预定宽度的开口，并且优选地被图案化以形成具有小于德拜筛选长度的尺寸的狭缝阵列。 这使得能够以不希望的方式避免衬底的离子轰击，从而控制衬底/等离子体相互作用时间。 快门和基板之间的相对位置可以通过移动快门或移动基板来进行。

公开(公告)号：US08536630B2

公开(公告)日：2013-09-17

申请号：US13301274

申请日：2011-11-21

申请人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

发明人： John C. Arnold ,  Xuefeng Hua ,  Rangarajan Jagannathan ,  Stefan Schmitz

IPC分类号： H01L29/772

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

摘要翻译： 在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间​​的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。