公开(公告)号：US20100062596A1

公开(公告)日：2010-03-11

申请号：US12591162

申请日：2009-11-10

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

摘要： In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

摘要翻译： 在形成N型MOS晶体管和P型MOS晶体管的半导体衬底中，N型MOS晶体管的栅电极包括与栅极绝缘膜接触的钨膜和栅电极 的P型MOS晶体管包括与栅极绝缘膜接触的钨膜，前者钨膜中所含的碳的浓度小于后者钨膜中所含的碳的浓度。

公开(公告)号：US07667274B2

公开(公告)日：2010-02-23

申请号：US12071887

申请日：2008-02-27

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L29/45 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.

摘要翻译： 公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层 通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层 所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数 第一金属硅化物层。

公开(公告)号：US20090203181A1

公开(公告)日：2009-08-13

申请号：US12320655

申请日：2009-01-30

申请人： Kyoichi Suguro ,  Mitsuaki Izuha

发明人： Kyoichi Suguro ,  Mitsuaki Izuha

IPC分类号： H01L21/336

CPC分类号： H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

摘要翻译： 在本发明的实施例中，通过热处理形成具有分别引入p型杂质，n型杂质和（p + n）杂质的区域的半导体层作为表面层。 除去这些区域上的杂质偏析层，然后在该区域上形成金属材料膜，并进行热处理，从而在半导体层上形成硅化物膜。 在另一个实施方案中，将杂质引入杂质偏析层中，然后在杂质偏析层上形成金属材料膜，并进行热处理以形成硅化物膜。

公开(公告)号：US07354819B2

公开(公告)日：2008-04-08

申请号：US10701435

申请日：2003-11-06

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L21/8238

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.

摘要翻译： 公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层 通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层 所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数 第一金属硅化物层。

公开(公告)号：US07327013B2

公开(公告)日：2008-02-05

申请号：US10743522

申请日：2003-12-23

申请人： Takeshi Shibata ,  Kyoichi Suguro

发明人： Takeshi Shibata ,  Kyoichi Suguro

IPC分类号： H01L29/06

CPC分类号： G03F1/20 ,  G03F1/40

摘要： A drive unit is described for switching circuit breakers on and off, in particular disconnecting switches and/or grounding switches of medium-voltage switchgear. The drive unit includes a reversible d.c. motor and a switching device containing two separately drivable and interlocked reversing switches, one assigned to each direction of rotation of the d.c. motor, their contacts performing the current reversal on the windings of the d.c. motor as required to reverse the direction of rotation. The drive unit further includes power contactors whose contacts have the required switching capacity for load switching. The all-or-nothing relays and safety switches are implemented by uniform low-power relays representing the direction of rotation, each having at least two electrically isolated relay contacts connected in parallel and also having an equalizing capacitor connected in parallel to each. Such drive units are used in connection with switchgear for power transmission and distribution.

摘要翻译： 在模板掩模中，导电薄膜在其中具有第一开口。 在除了第一开口之外的导电薄膜的区域中形成绝缘膜。 在绝缘膜上形成导电支撑。 第二个开口穿过导电支撑和绝缘膜并到达导电薄膜的表面。 导电构件形成在第二开口中。 导电构件电连接导电支撑件和导电薄膜。

公开(公告)号：US07279405B2

公开(公告)日：2007-10-09

申请号：US10980232

申请日：2004-11-04

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和 漏区。

公开(公告)号：US20070215918A1

公开(公告)日：2007-09-20

申请号：US11704924

申请日：2007-02-12

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US20070166977A1

公开(公告)日：2007-07-19

申请号：US11644887

申请日：2006-12-26

申请人： Hiroshi Itokawa ,  Yoshimasa Kawase ,  Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

发明人： Hiroshi Itokawa ,  Yoshimasa Kawase ,  Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.

摘要翻译： 公开了半导体器件制造方法。 首先在含硅半导体衬底的表面上形成含硅栅电极。 然后，在栅电极的侧壁上形成侧壁绝缘膜，并且在半导体衬底上形成金属膜以覆盖栅电极和侧壁绝缘膜。 通过环境气体的热传导来加热半导体衬底的正面和背面。 由此，使金属与包含在半导体衬底和栅电极中的硅反应，形成金属硅化物膜。

公开(公告)号：US20070052039A1

公开(公告)日：2007-03-08

申请号：US11512187

申请日：2006-08-30

申请人： Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

发明人： Toshihiko Iinuma ,  Haruko Akutsu ,  Kyoichi Suguro

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L23/48 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.

摘要翻译： 半导体器件包括包含Si的硅区域和设置在硅区域上的硅化物膜，该硅化物膜包含Si与Ni，Co，Pd或Pt的化合物并包括Er的化合物。

公开(公告)号：US07157340B2

公开(公告)日：2007-01-02

申请号：US11052861

申请日：2005-02-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kanna Tomiie ,  Kazuya Ouchi

IPC分类号： H01L21/336 ,  H01L21/331 ,  H01L21/332

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/6659

摘要： A manufacturing method of a semiconductor device, the method including implanting impurity ions into a silicon layer and irradiating a pulsed light having a pulse width of 100 milliseconds or less and a rise time of 0.3 milliseconds or more onto the silicon layer thereby activating the impurity ions. The rise time is defined as a time interval of a leading edge between an instant at which the pulsed light starts to rise and an instant at which the pulsed light reaches a peak energy.

摘要翻译： 一种半导体器件的制造方法，所述方法包括将杂质离子注入到硅层中，并将脉冲宽度为100毫秒或更短的脉冲光和0.3毫秒或更长的上升时间照射到硅层上，从而激活杂质离子 。 上升时间被定义为脉冲光开始上升的瞬间与脉冲光达到峰值能量的瞬间之间的前沿的时间间隔。