公开(公告)号：US20100308341A1

公开(公告)日：2010-12-09

申请号：US12745133

申请日：2008-09-08

申请人： Yoshiyuki Suda ,  Yutaka Ota

发明人： Yoshiyuki Suda ,  Yutaka Ota

IPC分类号： H01L29/24

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L21/8213 ,  H01L27/1021 ,  H01L27/1022 ,  H01L27/24

摘要： A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.

摘要翻译： 实现高集成度以及减少读出时间的开关电阻RAM。 形成由N阱11构成的集电极构成的NPN型双极晶体管BT，在N阱11的表面形成的由P +型Si层12A构成的基极层和由N阱11的表面形成的发射极层 形成在P +型Si层12A的表面上的N +型Si层15。 而且，形成与N +型Si层15电连接的字线WL0，与字线WL0相交的位线BL1〜BL4。 此外，形成在P +型Si层12A的表面上形成的多个开关层14，其各自与对应的每个位线电连接，并且在导通状态和断开状态之间切换以及电位固定线 19A以将P +型Si层12A固定在预定电位。

公开(公告)号：US06618545B1

公开(公告)日：2003-09-09

申请号：US09419284

申请日：1999-10-15

申请人： Yo Egusa ,  Yutaka Ota

发明人： Yo Egusa ,  Yutaka Ota

IPC分类号： H04N591

CPC分类号： H04N5/9206 ,  G11B27/002 ,  G11B27/107 ,  G11B27/11 ,  G11B27/3054 ,  G11B27/328 ,  G11B27/34 ,  G11B2220/90

摘要： A digital recording and reproducing apparatus comprising a cassette number registering circuit (1) for applying different CIDs for respective cassettes, a corresponding control circuit (7) for searching, adding and deleting program data, a cassette number inserting circuit (2) for inserting a CID in the form of a digital signal into the VBI of an analog video signal, a cassette number extracting circuit (3) for extracting a CID from a VBI, magnetic recording and reproducing means (4) for recording and reproducing the analog signal by using a magnetic tape (50), a display number registering circuit (5) for applying an AID which corresponds to a CID and is recognized by a user, a memory circuit (6) for storing program data including a CID, an AID, a starting tape position, an ending tape position and recording start date, a program integrating circuit (76) which makes one AID corresponds to a plurality of CIDs, and, keeps programs having later date and deletes programs having older date when the recorded magnetic tape positions of the recorded programs under the plurality of CIDs overlap. The above structure enable amendment when a plurality of CIDs are registered for one cassette by mistake. In integration, an AID of smaller number is selected. (FIG. 8)

摘要翻译： 一种数字记录和再现装置，包括用于对各个盒施加不同CID的盒号登记电路（1），用于搜索，添加和删除节目数据的相应控制电路（7），用于插入 将数字信号的形式的CID转换为模拟视频信号的VBI，用于从VBI提取CID的磁带盒号提取电路（3），用于通过使用来记录和再现模拟信号的磁记录和再现装置（4） 一个磁带（50），一个显示号码注册电路（5），用于应用与CID相对应并被用户识别的AID;存储电路（6），用于存储包括CID，AID，起始 磁带位置，结束磁带位置和记录开始日期，使一个AID对应于多个CID的程序集成电路（76），并且保持具有较后日期的程序并删除具有较旧日期的程序 当多个CID下记录的节目的记录磁带位置重叠时。 当多个CID被错误地注册到一个盒时，上述结构能够进行修改。 在集成中，选择较小数量的AID。 （图8）

公开(公告)号：US07946723B2

公开(公告)日：2011-05-24

申请号：US11667397

申请日：2005-10-24

申请人： Takashi Oku ,  Takeo Arai ,  Yutaka Ota ,  Yasuhiro Tagawa

发明人： Takashi Oku ,  Takeo Arai ,  Yutaka Ota ,  Yasuhiro Tagawa

IPC分类号： G09F13/04

CPC分类号： G02F1/133603 ,  G02F1/133608 ,  G02F1/133609 ,  G02F1/133611

摘要： Disclosed is a backlight device for illuminating a transmissive color liquid crystal display panel from its backside with white light. The backlight device includes, as a light source, a plural number of principal light emitting diode units 21mn, and a plural number of subsidiary light emitting diode units 21mn, where m and n are natural numbers. Each principal light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of preset chromaticity. Each subsidiary light emitting diode unit is made up by a plural number of light emitting diodes (21) arrayed in a string and emits white light of chromaticity in the vicinity of the preset chromaticity. The number of the subsidiary light emitting diode units is smaller than that of the principal light emitting diode units. When the principal light emitting diode units and the subsidiary light emitting diode units are arrayed in a two-dimensional matrix, the subsidiary light emitting diode units 21mn are arrayed without being juxtaposed on the same row, and the subsidiary light emitting diode units 21mn, arrayed in a center column of the two-dimensional matrix, are arrayed towards the center of a color liquid crystal display panel (110).

摘要翻译： 公开了一种背光装置，其用白光从其背面照射透射彩色液晶显示面板。 背光装置包括多个主发光二极管单元21mn和多个辅助发光二极管单元21mn作为光源，其中m和n是自然数。 每个主要发光二极管单元由排列成串的多个发光二极管（21）构成并发出预定色度的白光。 每个辅助发光二极管单元由排列成串的多个发光二极管（21）构成，并在预设色度附近发出色度的白光。 辅助发光二极管单元的数量小于主要发光二极管单元的数量。 当主发光二极管单元和辅助发光二极管单元被排列成二维矩阵时，辅助发光二极管单元21mn被排列而不并置在同一行上，并且辅助发光二极管单元21mn排列 在二维矩阵的中心列中朝向彩色液晶显示面板（110）的中心排列。

公开(公告)号：US20110055818A1

公开(公告)日：2011-03-03

申请号：US12713817

申请日：2010-02-26

申请人： Yuji ISHIKAWA ,  Yutaka Ota ,  Yu Nakanishi

发明人： Yuji ISHIKAWA ,  Yutaka Ota ,  Yu Nakanishi

IPC分类号： G06F9/44

CPC分类号： G06F8/51

摘要： Every time an assignment statement is executed during performing a simulation according to a second variable memory system, it is determined whether a value interpreted to have the same meaning is assigned to the assignment statement in the simulation according to a first variable memory system and in the simulation according to the second variable memory system. When the value interpreted to have the same meaning is not assigned, the value assigned according to the second variable memory system is overwritten by an expected value, and a report indicating that the assignment statement is a part dependent on a variable memory system is output.

摘要翻译： 在根据第二可变存储器系统执行仿真期间每次执行分配语句时，根据第一可变存储器系统确定在模拟中是否将解释为具有相同含义的值分配给模拟中的赋值语句，并且在 根据第二个可变存储器系统进行仿真。 当被解释为具有相同含义的值被分配时，根据第二变量存储器系统分配的值被预期值覆盖，并且输出指示分配语句是依赖于可变存储器系统的部分的报告。

公开(公告)号：US20090138862A1

公开(公告)日：2009-05-28

申请号：US12211420

申请日：2008-09-16

申请人： Ken Tanabe ,  Yutaka Ota ,  Nobu Matsumoto

发明人： Ken Tanabe ,  Yutaka Ota ,  Nobu Matsumoto

IPC分类号： G06F9/45

CPC分类号： G06F8/456

摘要： A program parallelization supporting apparatus determines a determinacy in at least one dependency relationship of a data dependency, a control dependency and a pointer dependency in a program, extracts a critical path in the program, and extracts a processing instruction which exists on the critical path and has a non-deterministic determinacy in the dependency relationship. Furthermore, if a process related to a path of the extracted non-deterministic processing instruction is parallelized and the path of the non-deterministic processing instruction is deleted, the program parallelization supporting apparatus outputs parallelization labor hour information depending on the number of dependency relationships disturbing the parallelization and parallelization effect information depending on the number of processing instructions which are shortened by the parallelization.

摘要翻译： 程序并行化支持装置确定程序中数据依赖性，控制依赖性和指针相关性的至少一个依赖关系的确定性，提取程序中的关键路径，并提取存在于关键路径上的处理指令， 在依赖关系中具有非确定性的确定性。 此外，如果与所提取的非确定性处理指令的路径相关的处理被并行并且删除非确定性处理指令的路径，则程序并行化支持装置根据依赖关系的数量来输出并行劳动时间信息 并行化和并行效应信息取决于通过并行化缩短的处理指令的数量。

公开(公告)号：US06074202A

公开(公告)日：2000-06-13

申请号：US218014

申请日：1998-12-22

申请人： Shin-Ichiro Yagi ,  Yutaka Ota

发明人： Shin-Ichiro Yagi ,  Yutaka Ota

IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/54 ,  H01L21/00 ,  H01L21/205 ,  H01L21/677 ,  F27D3/00

CPC分类号： H01L21/67017 ,  H01L21/67201 ,  H01L21/67253

摘要： An apparatus for manufacturing a semiconductor material includes a load-lock chamber which can contain a cassette for holding at least one wafer for taking the wafer into or out of the apparatus, a process furnace for conducting a treatment to the wafer, and a transfer chamber for transferring the wafer between the load-lock chamber and the process furnace, wherein the apparatus further includes a pressure detector for detecting a pressure difference between in the process furnace and in the transfer chamber, and a gas flow controller for controlling a flow rate of a gas flow supplied to the transfer chamber in accordance with results of detection by the pressure detector.

摘要翻译： 一种用于制造半导体材料的装置包括一个装载锁定室，它可以容纳用于保持至少一个晶片的盒，用于将晶片带入或移出该装置，一个用于对晶片进行处理的处理炉和一个传送室 用于在所述装载锁定室和所述处理炉之间传送所述晶片，其中所述装置还包括用于检测所述处理炉和所述传送室中的压力差的压力检测器和用于控制所述处理炉中的流量的气体流量控制器 根据压力检测器的检测结果向输送室供给气流。

公开(公告)号：US20100301301A1

公开(公告)日：2010-12-02

申请号：US12745146

申请日：2008-09-08

申请人： Yoshiyuki Suda ,  Yutaka Ota

发明人： Yoshiyuki Suda ,  Yutaka Ota

IPC分类号： H01L45/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/35 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/24 ,  Y10S438/931

摘要： There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.

摘要翻译： 提供了一个开关电阻RAM，在占用面积上大大减少，并且高度集成。 对应于字线WL0和WL1以及位线BL0和BL1的四个交点形成存储单元CEL11-CEL14。 每个存储单元CEL11-CEL14由形成在N +型Si层11的表面上的开关层13构成。开关层13通过电极14与上述位线BL0或BL1电连接。开关层 13由层叠在N +型Si层11的表面上的SiC层13A和层叠在SiC层13A上的Si氧化物层13B构成。 作为开关层13的最上层的Si氧化物层13B的上表面电连接到对应的位线BL0或BL1。

公开(公告)号：US07719852B2

公开(公告)日：2010-05-18

申请号：US11968716

申请日：2008-01-03

申请人： Shigeyuki Horie ,  Yutaka Ota ,  Jun Nishikawa

发明人： Shigeyuki Horie ,  Yutaka Ota ,  Jun Nishikawa

IPC分类号： H05K1/18

CPC分类号： H01G4/2325 ,  H01C1/148 ,  H01C7/18 ,  H01G4/30 ,  Y10T428/24917

摘要： A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 μm or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C. inclusive in a reducing atmosphere having an oxygen concentration of about 100 ppm or less.

摘要翻译： 在高温高湿条件下绝缘电阻降低的高可靠性电子元件具有良好的外部电极的可焊性。 电子部件包括主体和设置在主体表面上的外部电极，外部电极包括各自包含金属的下部电极层，各自设置在相应的下部电极层上的合金层，各自设置在相应的合金上的Ni镀层 各自设置在相应的Ni镀层上的Ni氧化物层和分别设置在相应的Ni氧化物层上的上部镀层，每个Ni氧化物层的厚度为约150nm以下，并且每个Ni镀层具有平均粒子 Ni颗粒的尺寸约为2μm或更大。 为了形成具有减小的晶界的Ni镀层，在约500℃至约900℃（包括在氧浓度为约100ppm或更低的还原气氛中）进行热处理。

公开(公告)号：US07657878B2

公开(公告)日：2010-02-02

申请号：US10807374

申请日：2004-03-24

申请人： Yutaka Ota

发明人： Yutaka Ota

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A compiler includes: a syntax analyzer analyzing whether or not an operation described in a source program conforms to grammatical rules, and analyzing whether or not a combination of the operations defines an intrinsic function and details of processing operations of the intrinsic function; an intrinsic function definition database storing a definition of the intrinsic function and the details of the processing operations of the intrinsic function, as analyzed by the syntax analyzer; a code generator generating machine instructions from the source program based on a result of the processing of the syntax analyzer; and a code optimizer optimizing the machine instructions to machine instructions corresponding to the details of the processing operations of the intrinsic function, if a string of the machine instructions generated by the code generator are in agreement with the details of the processing operations of the intrinsic function stored in the intrinsic function definition database.

摘要翻译： 编译器包括：分析源程序中描述的操作是否符合语法规则的语法分析器，以及分析操作的组合是否定义了内在函数的内在函数和处理操作的细节; 固有功能定义数据库，存储由语法分析器分析的内在函数的定义和内在函数的处理操作的细节; 代码生成器，基于语法分析器的处理结果从源程序生成机器指令; 以及代码优化器，如果由代码生成器生成的机器指令的字符串与内在函数的处理操作的细节一致，则优化机器指令以对与本征函数的处理操作的细节相对应的机器指令进行优化 存储在内在函数定义数据库中。

公开(公告)号：US20080186433A1

公开(公告)日：2008-08-07

申请号：US11631543

申请日：2005-07-12

申请人： Shuichi Haga ,  Koichiro Kakinuma ,  Takehiro Nakatsue ,  Tatsuhiko Matsumoto ,  Yasuhiro Tagawa ,  Yutaka Ota ,  Takashi Oku ,  Takeo Arai

发明人： Shuichi Haga ,  Koichiro Kakinuma ,  Takehiro Nakatsue ,  Tatsuhiko Matsumoto ,  Yasuhiro Tagawa ,  Yutaka Ota ,  Takashi Oku ,  Takeo Arai

IPC分类号： G02F1/1335

CPC分类号： G02B5/201 ,  G02F1/133514 ,  G02F2001/133624

摘要： A color filter (19) used in a transmissive color liquid crystal display panel of a color liquid crystal display (LCD) apparatus. This color filter (19) is constituted by a tristimulus color filter for wavelength-selecting and transmitting red light, green light and blue light. Mixing of blue color and red color is prohibited by not having the transmission wavelength band of the red filter CFR overlaid substantially on the transmission wavelength band of the blue filter CFB.

摘要翻译： 一种在彩色液晶显示器（LCD）装置的透射彩色液晶显示面板中使用的滤色器（19）。 该滤色器（19）由用于波长选择和透射红光，绿光和蓝光的三色滤色器构成。 红色滤光片CFR的透过波长带基本上不叠加在蓝色滤光器CFB的透射波长带上，因此禁止混合蓝色和红色。