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    SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS
    12.
    发明申请
    SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS 有权
    可分配的分布式存储器和I / O多处理器系统及相关方法

    公开(公告)号：US20090319717A1

    公开(公告)日：2009-12-24

    申请号：US12549491

    申请日：2009-08-28

    申请人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    发明人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

    摘要翻译： 多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。 互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。 标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。 此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线，时钟和复位逻辑都保持不变。

    Scalable distributed memory and I/O multiprocessor systems and associated methods
    13.
    发明授权
    Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
    可扩展分布式存储器和I / O多处理器系统及相关方法

    公开(公告)号：US07603508B2

    公开(公告)日：2009-10-13

    申请号：US12013595

    申请日：2008-01-14

    申请人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    发明人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

    摘要翻译： 多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。 互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。 标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。 此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线，时钟和复位逻辑都保持不变。

    Scalable distributed memory and I/O multiprocessor systems and associated methods
    14.
    发明授权
    Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
    可扩展分布式存储器和I / O多处理器系统及相关方法

    公开(公告)号：US07343442B2

    公开(公告)日：2008-03-11

    申请号：US11422542

    申请日：2006-06-06

    申请人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    发明人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

    摘要翻译： 多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。 互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。 标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。 此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线，时钟和复位逻辑都保持不变。

    Method to prefetch data from system memory using a bus interface unit
    15.
    发明授权
    Method to prefetch data from system memory using a bus interface unit 失效
    使用总线接口单元从系统存储器预取数据的方法

    公开(公告)号：US06718441B2

    公开(公告)日：2004-04-06

    申请号：US10141231

    申请日：2002-05-08

    申请人： Mark A. Gonzales ,  Linda J. Rankin

    发明人： Mark A. Gonzales ,  Linda J. Rankin

    IPC分类号： G06F1300

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3824 ,  G06F12/0862 ,  G06F2212/6022

    摘要： A method and system to prefetch data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected to a high speed bus, a CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and speculative or prefetch information. When the CPU generates a subsequent request, the interface compares the addresses requested with the addresses in the prefetch buffer. If the buffer contains the addresses, the data is sent to the processor. The prefetch buffer is directly addressable so that any line within the buffer can be retrieved.

    摘要翻译： 从系统存储器向中央处理单元（CPU）预取数据的方法和系统。 该系统包括连接到高速总线的动态随机存取存储器（DRAM），CPU和总线接口单元，其允许CPU与高速总线通信。 总线接口单元包含逻辑电路，使得当CPU产生与第一地址相关联的信息的读取存储器访问请求时，接口单元生成用于信息的请求包并且预取与预取地址相关联的信息。 总线接口单元通过增加CPU最初请求的地址数来创建请求包。 然后，该接口将请求分组发送到系统存储器设备，该设备检索并返回所请求的数据。 接口可以包括一对缓冲器，其存储由CPU请求的信息和推测或预取信息。 当CPU产生后续请求时，接口将请求的地址与预取缓冲区中的地址进行比较。 如果缓冲区包含地址，则将数据发送到处理器。 预取缓冲区可直接寻址，以便可以检索缓冲区内的任何行。

    Computer system having a bus interface unit for prefetching data from system memory
    16.
    发明授权
    Computer system having a bus interface unit for prefetching data from system memory 失效
    计算机系统具有用于从系统存储器预取数据的总线接口单元

    公开(公告)号：US06453388B1

    公开(公告)日：2002-09-17

    申请号：US08438473

    申请日：1995-05-10

    申请人： Mark A. Gonzales ,  Linda J. Rankin

    发明人： Mark A. Gonzales ,  Linda J. Rankin

    IPC分类号： G06F1300

    CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3824 ,  G06F12/0862 ,  G06F2212/6022

    摘要： A computer system, a bus interface unit, and a method for prefetching data from system memory to a central processing unit (CPU). The system includes a dynamic random access memory (DRAM) connected to a high speed bus, a CPU and a bus interface unit that allows the CPU to communicate with the high speed bus. The bus interface unit contains logic circuitry, so that when the CPU generates a read memory access request for information associated with a first address, the interface unit generates a request a packet for the information and prefetch information associated with a prefetch address. The bus interface unit creates the request packet by increasing the number of addresses originally requested by the CPU. The interface then sends the request packet to the system memory device, which retrieves and returns the requested data. The interface may include a pair of buffers which store both the information requested by the CPU and speculative or prefetch information. When the CPU generates a subsequent request, the interface compares the addresses requested with addresses in the prefetch buffer. If the buffer contains the addresses, the data is sent to the processor. The prefetch buffer is directly addressable so that any line within the buffer can be retrieved.

    摘要翻译： 一种计算机系统，总线接口单元以及用于将数据从系统存储器预取到中央处理单元（CPU）的方法。 该系统包括连接到高速总线的动态随机存取存储器（DRAM），CPU和总线接口单元，其允许CPU与高速总线通信。 总线接口单元包含逻辑电路，使得当CPU产生与第一地址相关联的信息的读取存储器访问请求时，接口单元产生用于信息的分组和预取与预取地址相关联的信息的请求。 总线接口单元通过增加CPU最初请求的地址数来创建请求包。 然后，该接口将请求分组发送到系统存储器设备，该设备检索并返回所请求的数据。 接口可以包括一对缓冲器，其存储由CPU请求的信息和推测或预取信息。 当CPU产生后续请求时，接口将比较预取缓冲区中与地址相对应的地址。 如果缓冲区包含地址，则将数据发送到处理器。 预取缓冲区可直接寻址，以便可以检索缓冲区内的任何行。

    CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval
    17.
    发明授权
    CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval 失效
    如果连接到快速总线的I / O设备在预定的时间间隔后没有对读取请求进行确认，则CPU从慢速总线读取数据

    公开(公告)号：US5898894A

    公开(公告)日：1999-04-27

    申请号：US826319

    申请日：1997-03-27

    申请人： David R. Gray ,  Mark A. Gonzales ,  Linda J. Rankin

    发明人： David R. Gray ,  Mark A. Gonzales ,  Linda J. Rankin

    IPC分类号： G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4252

    摘要： A computer architecture that includes a high speed, low pin bus that directly couples a microprocessor to the physical memory of the processor. Physical memory typically has a number of dynamic random access memory (DRAM) devices. The bus is a byte wide and has a data rate of approximately 500 Mbytes/sec. The high speed bus may be coupled with a conventional bus, so that conventional devices can communicate with the processor using existing bus protocols. The present invention includes a processor interface that allows the processor to communicate using the protocol of either bus. The interface also allows communication between devices on either bus. Also included is a system that incorporates cache memory on a high speed memory bus and a method for allowing I/O devices to be placed on both a conventional bus and the separate high speed bus.

    摘要翻译： 一种包括将微处理器直接耦合到处理器的物理存储器的高速，低引脚总线的计算机架构。 物理存储器通常具有多个动态随机存取存储器（DRAM）器件。 总线宽字节，数据速率约为500兆字节/秒。 高速总线可以与常规总线耦合，使得常规设备可以使用现有总线协议与处理器通信。 本发明包括允许处理器使用任一总线的协议进行通信的处理器接口。 该接口还允许在任一总线上的设备之间进行通信。 还包括一种在高速存储器总线上集成高速缓冲存储器的系统，以及允许将I / O设备放置在常规总线和单独的高速总线上的方法。

    Method and apparatus for providing remote memory access in a distributed memory multiprocessor system
    18.
    发明授权
    Method and apparatus for providing remote memory access in a distributed memory multiprocessor system 失效
    用于在分布式存储器多处理器系统中提供远程存储器访问的方法和装置

    公开(公告)号：US5613071A

    公开(公告)日：1997-03-18

    申请号：US502071

    申请日：1995-07-14

    申请人： Linda J. Rankin ,  Joseph Bonasera ,  Nitin Y. Borkar ,  Linda C. Ernst ,  Suvansh K. Kapur ,  Daniel A. Manseau ,  Frank Verhoorn

    发明人： Linda J. Rankin ,  Joseph Bonasera ,  Nitin Y. Borkar ,  Linda C. Ernst ,  Suvansh K. Kapur ,  Daniel A. Manseau ,  Frank Verhoorn

    IPC分类号： G06F12/02 ,  G06F15/173

    CPC分类号： G06F15/17381 ,  G06F12/0284

    摘要： A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.

    摘要翻译： 公开了一种大规模并行的数据处理系统。 该数据处理系统包括多个节点，每个节点具有至少一个处理器，用于存储数据的存储器，将处理器耦合到存储器的处理器总线以及耦合到处理器总线的远程存储器访问控制器。 远程存储器访问控制器检测和排队处理器对远程存储器的请求，将处理器请求处理和打包成请求包，通过与该节点对应的路由器将请求包转发到网络，接收并排队从网络接收的请求包， 从请求分组恢复存储器请求，根据请求操纵本地存储器，生成可接受的适当的响应分组，并将响应分组转发到请求节点。

    SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM
    20.
    发明申请
    SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
    可分配的分布式存储器和I / O多处理器系统

    公开(公告)号：US20120317328A1

    公开(公告)日：2012-12-13

    申请号：US13590936

    申请日：2012-08-21

    申请人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    发明人： Linda J. Rankin ,  Paul R. Pierce ,  Gregory E. Dermer ,  Wen-Hann Wang ,  Kai Cheng ,  Richard H. Hofsheier ,  Nitin Y. Borkar

    IPC分类号： G06F13/28 ,  G06F13/00

    CPC分类号： G06F13/4022 ,  G06F13/4027

    摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

    摘要翻译： 多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。 在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。 互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。 使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。 标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。 此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。 处理器内存总线，时钟和复位逻辑都保持不变。