公开(公告)号：US5263251A

公开(公告)日：1993-11-23

申请号：US1384

申请日：1993-01-06

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： F28F3/12 ,  H01L23/473 ,  B23P15/26

CPC分类号： H01L23/473 ,  F28F3/12 ,  F28F2260/02 ,  H01L2924/0002 ,  Y10T29/49361 ,  Y10T29/49995

摘要： A method of making an ultra compact laminar-flow heat exchanger includes forming microscopic regions along the front side of an elongated ribbon of material and spirally laminating the ribbon into a core wherein the front side abuts the backside of the ribbon, thereby forming enclosed microscopic channels.

摘要翻译： 制造超紧凑型层流式热交换器的方法包括沿着细长的材料带的前侧形成微观区域，并将带状物螺旋地层压到芯中，其中前侧邻接带的背面，由此形成封闭的微细通道 。

公开(公告)号：US5232047A

公开(公告)日：1993-08-03

申请号：US820365

申请日：1992-01-14

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： F28F3/12 ,  H01L23/473

CPC分类号： F28F3/12 ,  H01L23/473 ,  F28F2260/02 ,  H01L2924/0002

摘要： A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

摘要翻译： 适用于冷却诸如半导体集成电路的发热装置的微型层流式热交换器包括多个薄板，层压在一起以形成块体。 每个板具有蚀刻到板的一个面中的微观凹陷部分和穿过板切割的一对孔，使得当形成块时，孔对准以形成一对冷却剂分配歧管。 在层压过程中，歧管通过由凹部形成的多个微细通道相连接。 通过这些通道的冷却液流动可实现除热。

公开(公告)号：US5108945A

公开(公告)日：1992-04-28

申请号：US647709

申请日：1991-01-28

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC分类号： H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

摘要： A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

摘要翻译： 耦合到硅衬底中的MOS场效应器件的多晶硅电阻器和多晶硅互连件的处理过程包括沉积和蚀刻第一多晶硅层以形成MOS器件的栅极的步骤; 然后在所述栅极之间沉积第二层多晶硅。 然后蚀刻第二多晶硅层，使得其上表面与栅极基本上共面。 然后通过形成在第一和第二多晶硅层上的绝缘层将接触开口限定到器件的源极，漏极和栅极部件。 接下来，沉积金属层以填充开口并被图案化以限定到器件的电触点。 图案化步骤还限定了金属层中的互连线。 然后沉积和图案化第三多晶硅层以限定多晶硅电阻器和互连。

公开(公告)号：US06379545B1

公开(公告)日：2002-04-30

申请号：US09645294

申请日：2000-08-24

申请人： Johan A. Perslow ,  Mark E. Krebs ,  James A. Matthews

发明人： Johan A. Perslow ,  Mark E. Krebs ,  James A. Matthews

IPC分类号： C02F300

CPC分类号： C02F3/1263 ,  C02F1/78 ,  C02F11/02 ,  C02F2303/24 ,  Y02W10/15 ,  Y02W10/27

摘要： A modular system for treating wastewater is designed having different phases. In an initial phase, plural tanks are provided, including at least one reactor and digester tank. In a subsequent phase, at least one of the tanks is converted into a different type of tank, and additional new tanks are provided to accommodate larger quantities of wastewater. In one embodiment, conversion of at least one of the tanks is accomplished by removing a temporary wall from a digester tank to create another reactor tank.

摘要翻译： 用于处理废水的模块化系统设计具有不同的相位。 在初始阶段，提供多个罐，包括至少一个反应器和蒸煮罐。 在随后的阶段中，至少一个罐被转换成不同类型的罐，并且提供另外的新罐以容纳更大量的废水。 在一个实施例中，通过从蒸煮罐移除临时壁以产生另一个反应器罐来实现至少一个罐的转化。

公开(公告)号：US6132614A

公开(公告)日：2000-10-17

申请号：US168543

申请日：1998-10-08

申请人： Johan A. Perslow ,  Mark E. Krebs ,  James A. Matthews

发明人： Johan A. Perslow ,  Mark E. Krebs ,  James A. Matthews

IPC分类号： C02F1/78 ,  C02F3/12 ,  C02F11/02 ,  C02F3/00

CPC分类号： C02F3/1263 ,  C02F11/02 ,  C02F1/78 ,  C02F2303/24 ,  Y02W10/15 ,  Y02W10/27

摘要： A modular system for treating wastewater is designed having different phases. In an initial phase, plural tanks are provided, including at least one reactor and digester tank. In a subsequent phase, at least one of the tanks is converted into a different type of tank, and additional new tanks are provided to accommodate larger quantities of wastewater. In one embodiment, conversion of at least one of the tanks is accomplished by removing a temporary wall from a digester tank to create another reactor tank.

公开(公告)号：US5274920A

公开(公告)日：1994-01-04

申请号：US820366

申请日：1992-01-14

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： F28F3/04 ,  F28F3/12 ,  H01L23/473 ,  B23P15/26

CPC分类号： F28F3/12 ,  H01L23/473 ,  F28D2021/0029 ,  F28F2260/02 ,  H01L2924/0002 ,  Y10T29/49366 ,  Y10T29/49368

摘要： A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

摘要翻译： 适于冷却诸如半导体集成电路的发热装置的微型层流式热交换器包括多个薄板，层压在一起以形成块体。 每个板具有蚀刻到板的一个面中的微观凹陷部分和穿过板切割的一对孔，使得当形成块时，孔对准以形成一对冷却剂分配歧管。 在层压过程中，歧管通过由凹部形成的多个微细通道相连接。 通过这些通道的冷却液流动可实现除热。

公开(公告)号：US5256505A

公开(公告)日：1993-10-26

申请号：US933393

申请日：1992-08-21

申请人： Jang F. Chen ,  James A. Matthews

发明人： Jang F. Chen ,  James A. Matthews

IPC分类号： G03F1/00 ,  G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70433 ,  G03F1/36 ,  G03F7/70441

摘要： A mask for transferring square and rectangular features having critical dimensions (CDs) close to the resolution limit of the exposure tool utilized to perform the transference is described. Intensity modulation lines having the opposite transparency as the rectangular feature to be transferred, and a width significantly less than the resolution of the exposure tool, are disposed within the rectangular feature. The intensity modulation lines have the affect of damping intensity levels on the resist layer in the center of the rectangular feature. As a result, the final CD measurement of the rectangular feature is within the CD tolerance of the original designed CD measurement. In addition, since modulation lines are have dimensions well below the resolution limit of the exposure tool, they are not seen in the final rectangular resist pattern.

摘要翻译： 描述用于传送具有接近用于执行转移的曝光工具的分辨率极限的临界尺寸（CD）的正方形和矩形特征的掩模。 具有与要传送的矩形特征相反的透明度的强度调制线和明显小于曝光工具的分辨率的宽度被布置在矩形特征内。 强度调制线具有矩形特征中心的抗蚀剂层上的阻尼强度水平的影响。 因此，矩形特征的最终CD测量在原始设计的CD测量的CD容差范围内。 此外，由于调制线的尺寸远远低于曝光工具的分辨率极限，所以在最终的矩形抗蚀剂图案中看不到。

公开(公告)号：US5242770A

公开(公告)日：1993-09-07

申请号：US821793

申请日：1992-01-16

申请人： Jang F. Chen ,  James A. Matthews

发明人： Jang F. Chen ,  James A. Matthews

IPC分类号： G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027

CPC分类号： G03F1/36 ,  G03F7/70433 ,  G03F7/70441

摘要： An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.

摘要翻译： 用于减少由附加线（称为强度调平条）组成的接近效应进入掩模图案的改进。 调平条执行调整掩模图案中孤立边缘的边缘强度梯度的功能，以匹配密集边缘的边缘强度梯度。 调平条平行于孤立的边缘放置，使得强度梯度平整发生在掩模图案的所有隔离边缘上。 此外，调平条被设计成具有明显小于曝光工具的分辨率的宽度。 因此，当在光致抗蚀剂的曝光期间使用标称曝光能量时，存在于掩模图案中的调平条产生完全展开的抗蚀剂图案。

公开(公告)号：US5171713A

公开(公告)日：1992-12-15

申请号：US647718

申请日：1991-01-28

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L29/417

CPC分类号： H01L21/28211 ,  H01L21/28525 ,  H01L21/7682 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/02

摘要： A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.

摘要翻译： 一种用于制造集成电路（IC）的方法，包括通过设置在半导体衬底上方的金属互连系统耦合在一起的多个器件，包括在衬底的表面上形成多个导电基座的步骤。 基座的一部分与设备形成电接触，其中基座的高度高于基板的任何特征。 在基板上沉积聚酰亚胺层至覆盖基座的厚度之后，进行蚀刻步骤直到基座的顶表面与聚酰亚胺层共面。 然后在聚酰亚胺和基座上形成一组金属互连线，以形成与所选择的基座接触件的电连接。

公开(公告)号：US5134083A

公开(公告)日：1992-07-28

申请号：US647707

申请日：1991-01-28

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC分类号： H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

摘要： A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required to the interconnection of the MOS and NPN transistors. Self-aligned interconnects are formed by patterning polysilicon, an insulative layer, And a silicide layer, using first silicide contacts over device components as etch stop.