公开(公告)号：US20100020864A1

公开(公告)日：2010-01-28

申请号：US12374994

申请日：2007-07-12

申请人： Michiaki Matsuo ,  Hitoshi Asano ,  Hideki Aoyagi ,  Kazuaki Takahashi ,  Yew Soo Eng

发明人： Michiaki Matsuo ,  Hitoshi Asano ,  Hideki Aoyagi ,  Kazuaki Takahashi ,  Yew Soo Eng

IPC分类号： H03K7/04 ,  H04L27/06

CPC分类号： H04L25/4906 ,  H04B1/7172 ,  H04B1/719 ,  H04L25/4902

摘要： A pulse transmitting device is provided to avoid interference between pulses due to multipath influence even in a high speed pulse transmission that is typical of a UWB by making use of a relatively simple method and to improve receiving quality. In the device, a pulse adjusting unit (110) generates pulses in response to transmitting data, a non-use interval setting unit (120) sets up a non-use interval where the pulses generated by the pulse adjusting unit (110) are not transmitted on the basis of a delay time that a delayed pulse caused by the multipath delays from a main pulse and takes until arriving at a communication partner. A pulse position adjusting unit (130) adjusts a pulse position not to transmit the pulses during the non-use pulse interval. An RF transmitting unit (140) converts the pulse, the position of which is adjusted by the pulse position adjusting unit, to a wireless frequency band and transmits a pulse wireless signal after the conversion to the communication partner.

摘要翻译： 提供脉冲发送装置，即使在UWB的典型的高速脉冲传输中，通过利用相对简单的方法并且提高接收质量，也可以避免由于多路径影响引起的脉冲之间的干扰。 在该装置中，脉冲调整单元（110）响应于发送数据产生脉冲，不使用间隔设定单元（120）设定由脉冲调整单元（110）生成的脉冲不是的非使用间隔 基于由主脉冲的多径延迟引起的延迟脉冲的延迟时间发送，并且直到到达通信伙伴。 脉冲位置调整单元（130）调整在不使用脉冲间隔期间不发送脉冲的脉冲位置。 RF发送单元（140）将其位置由脉冲位置调整单元调整的脉冲转换为无线频带，并且在转换到通信对方之后发送脉冲无线信号。

公开(公告)号：US07254125B2

公开(公告)日：2007-08-07

申请号：US10491573

申请日：2003-05-16

申请人： Akihiko Nishio ,  Hideki Aoyagi ,  Hiroki Haga

发明人： Akihiko Nishio ,  Hideki Aoyagi ,  Hiroki Haga

IPC分类号： H04B7/216

CPC分类号： H04B1/7113 ,  H04B1/70754 ,  H04B1/7085 ,  H04B1/7117

摘要： Using midambles, tracking delay profile creator 107 opens correlation windows in the range of 8 chips before and behind the top path and creates delay profiles within this range. From the delay profiles, path determiner 108 detects whether or not there is a new path before the top path, and, when there is a new path, determines whether or not this is its path. Based on the result of the determination at path determiner 108, when the new path is its path, frame position controller 109 sets the top path with the new path. On the other hand, when the new path is not its path, the top path set earlier is retained as is as the top path. Then, in accordance with the timing of the top path set, a received signal is demodulated. By this means, reception quality can be improved.

摘要翻译： 使用中间线，跟踪延迟分布创建器107在顶部路径之前和之后打开8个码片范围内的相关窗口，并在该范围内创建延迟曲线。 从延迟分布中，路径确定器108检测在顶部路径之前是否存在新路径，并且当存在新路径时，确定这是否是其路径。 基于路径确定器108的确定结果，当新路径是其路径时，帧位置控制器109设置具有新路径的顶部路径。 另一方面，当新路径不是其路径时，先前设置的顶部路径将保持与顶部路径一样。 然后，根据顶部路径的定时，对接收到的信号进行解调。 通过这种方式，可以提高接收质量。

公开(公告)号：US06896257B2

公开(公告)日：2005-05-24

申请号：US10662454

申请日：2003-09-16

申请人： Masashi Yamashita ,  Hideki Aoyagi ,  Atsumi Kobayashi

发明人： Masashi Yamashita ,  Hideki Aoyagi ,  Atsumi Kobayashi

IPC分类号： B65H9/14 ,  B65H3/06 ,  B65H9/10 ,  B65H9/04

CPC分类号： B65H9/006 ,  B65H2301/512125 ,  B65H2404/7231 ,  B65H2511/12 ,  B65H2511/17 ,  B65H2511/414 ,  B65H2220/01 ,  B65H2220/02

摘要： A sheet feeding apparatus includes a stacking tray for stacking a sheet, a sheet feeding device for feeding the sheet, a register device for aligning a leading edge of the sheet fed by the sheet feeding device, a recognition device for recognizing a state that the sheets stacked on the stacking tray have different widths, and a setting device for setting a feeding distance according to a result of the recognition device. A control device controls the sheet feeding device to feed the sheet for the feeding distance.

摘要翻译： 片材进给装置包括用于堆叠片材的堆垛托盘，用于进给片材的片材进给装置，用于对准由片材进给装置供给的片材的前缘的对准装置，识别装置，用于识别片材 堆叠在堆叠托盘上的宽度不同的设置装置，以及根据识别装置的结果来设定馈送距离的设定装置。 控制装置控制片材进给装置供给进给距离的片材。

公开(公告)号：US08755468B2

公开(公告)日：2014-06-17

申请号：US12374737

申请日：2007-07-27

申请人： Michiaki Matsuo ,  Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki

发明人： Michiaki Matsuo ,  Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki

IPC分类号： H04L27/06

CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/0812 ,  H04B1/717 ,  H04B1/7183 ,  H04L7/0037

摘要： A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.

摘要翻译： 基于开关键控调制方式的接收脉冲信号由频率为传输速率的二分之一的时钟信号操作的AD转换部分交替采样。 在同步中，采样定时调整部分中的延迟量彼此不同，从而对符号脉冲中两个不同点的相位进行采样。 根据采样值的比较结果调整可变延迟部分的延迟量，从而实现同步。 在解调时，保持可变延迟部分中的延迟量，并将采样定时调整部分中的延迟量切换到相同的值，并且对符号脉冲进行交替采样。 对采样值进行阈值判定，对判定结果进行并行到串行转换，从而得到解调输出。

公开(公告)号：US08358727B2

公开(公告)日：2013-01-22

申请号：US12438094

申请日：2007-09-26

申请人： Suguru Fujita ,  Hideki Aoyagi ,  Takenori Sakamoto

发明人： Suguru Fujita ,  Hideki Aoyagi ,  Takenori Sakamoto

IPC分类号： H04L7/00

CPC分类号： H04L7/0054 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0037 ,  H04L25/068

摘要： The present invention has an object to provide a wireless apparatus which is capable of correctly sampling a waveform of a pulse even when a shape of the pulse is varied.A synchronizing apparatus for causing an input signal to be synchronized with a clock signal is equipped with sampling unit 102, 103, and delay control unit 112. The sampling unit 102 and 103 sample the input signal at first sampling timing and second sampling timing, which are separated from each other in a predetermined time interval. The delay control unit 112 shifts both the first and second sampling timing during synchronous pull-in operation, and also, narrows the interval between said first and second sampling timing during synchronous follow-up operation. A synchronous status judging unit 105 judges whether or not the input signal is synchronized with the clock signal based upon a phase error amount outputted from a phase error calculating unit 104, and outputs the synchronous status to a delay amount control unit 106. The delay amount control unit 106 controls to increase/decrease delay amounts which have been presently set in variable delay devices 107 and 108 based upon the phase error amount outputted from the phase error calculating unit 104 and the synchronous status outputted from the synchronous status judging unit 105.

摘要翻译： 本发明的目的是提供一种即使当脉冲的形状改变时也能够正确地采样脉冲波形的无线装置。 用于使输入信号与时钟信号同步的同步装置配备有采样单元102,103和延迟控制单元112.采样单元102和103在第一采样定时和第二采样定时对输入信号进行采样，其中 在预定的时间间隔彼此分离。 延迟控制单元112在同步拉入操作期间移动第一和第二采样定时两者，并且在同步跟随操作期间也缩小所述第一和第二采样定时之间的间隔。 同步状态判断单元105基于从相位误差计算单元104输出的相位误差量判断输入信号是否与时钟信号同步，并将同步状态输出到延迟量控制单元106.延迟量 控制单元106基于从相位误差计算单元104输出的相位误差量和从同步状态判断单元105输出的同步状态来控制当前在可变延迟装置107和108中设置的延迟量的增减。

公开(公告)号：US08121201B2

公开(公告)日：2012-02-21

申请号：US12297561

申请日：2007-04-19

申请人： Hitoshi Asano ,  Hideki Aoyagi ,  Michiaki Matsuo

发明人： Hitoshi Asano ,  Hideki Aoyagi ,  Michiaki Matsuo

IPC分类号： H04B14/04

CPC分类号： H04L25/4902 ,  H04L7/0008 ,  H04L25/4917

摘要： A pulse transmitter having a relatively simple structure and generating a pulse modulating signal even at a high transmission rate. In the pulse transmitter, a symbol pulse generating part (103) generates a symbol pulse of amplitude level β when data S1 is “0,” and that of amplitude level &ggr; when data S1 is “1” in the first pulse slot section, the data pulse generating part (104) generates a data pulse of amplitude level 0 when data S2 to Sn is “0,” and that of amplitude level α when data S2 to Sn is “1” in a later pulse slot section. The relationship of the amplitude levels keep the relation α

摘要翻译： 一种具有相对简单结构并且即使在高传输速率也产生脉冲调制信号的脉冲发射机。 在脉冲发送器中，符号脉冲生成部（103）生成振幅电平“bgr”的符号脉冲， 当数据S1为“0”时，幅度电平为“g”; 当第一脉冲时隙部分的数据S1为“1”时，数据脉冲产生部分（104）当数据S2至Sn为“0”时产生振幅电平为0的数据脉冲，当数据S2至 Sn在稍后的脉冲槽部分中为“1”。 振幅水平的关系保持关系α<＆bgr; <＆ggr。 加法器（105）将符号脉冲和数据脉冲相加，并将该和作为脉冲调制信号输出。

公开(公告)号：US07898312B2

公开(公告)日：2011-03-01

申请号：US12376024

申请日：2007-08-07

申请人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

发明人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00058

摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

摘要翻译： 本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。 本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号 ，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。

公开(公告)号：US20100239058A1

公开(公告)日：2010-09-23

申请号：US12438094

申请日：2007-09-26

申请人： Suguru Fujita ,  Hideki Aoyagi ,  Takenori Sakamoto

发明人： Suguru Fujita ,  Hideki Aoyagi ,  Takenori Sakamoto

IPC分类号： H04L7/00

CPC分类号： H04L7/0054 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0037 ,  H04L25/068

摘要： The present invention has an object to provide a wireless apparatus which is capable of correctly sampling a waveform of a pulse even when a shape of the pulse is varied.A synchronizing apparatus for causing an input signal to be synchronized with a clock signal is equipped with sampling unit 102, 103, and delay control unit 112. The sampling unit 102 and 103 sample the input signal at first sampling timing and second sampling timing, which are separated from each other in a predetermined time interval. The delay control unit 112 shifts both the first and second sampling timing during synchronous pull-in operation, and also, narrows the interval between said first and second sampling timing during synchronous follow-up operation. A synchronous status judging unit 105 judges whether or not the input signal is synchronized with the clock signal based upon a phase error amount outputted from a phase error calculating unit 104, and outputs the synchronous status to a delay amount control unit 106. The delay amount control unit 106 controls to increase/decrease delay amounts which have been presently set in variable delay devices 107 and 108 based upon the phase error amount outputted from the phase error calculating unit 104 and the synchronous status outputted from the synchronous status judging unit 105.

摘要翻译： 本发明的目的是提供一种即使当脉冲的形状改变时也能够正确地采样脉冲波形的无线装置。 用于使输入信号与时钟信号同步的同步装置配备有采样单元102,103和延迟控制单元112.采样单元102和103在第一采样定时和第二采样定时对输入信号进行采样，其中 在预定的时间间隔彼此分离。 延迟控制单元112在同步拉入操作期间移动第一和第二采样定时两者，并且在同步跟随操作期间也缩小所述第一和第二采样定时之间的间隔。 同步状态判断单元105基于从相位误差计算单元104输出的相位误差量判断输入信号是否与时钟信号同步，并将同步状态输出到延迟量控制单元106.延迟量 控制单元106基于从相位误差计算单元104输出的相位误差量和从同步状态判断单元105输出的同步状态来控制当前在可变延迟装置107和108中设置的延迟量的增减。

公开(公告)号：US20090315605A1

公开(公告)日：2009-12-24

申请号：US12376024

申请日：2007-08-07

申请人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

发明人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00058

摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

摘要翻译： 本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。 本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号 ，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。