公开(公告)号：US20100246660A1

公开(公告)日：2010-09-30

申请号：US12374737

申请日：2007-07-27

申请人： Michiaki Matsuo ,  Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki

发明人： Michiaki Matsuo ,  Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki

IPC分类号： H03K9/04

CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/0812 ,  H04B1/717 ,  H04B1/7183 ,  H04L7/0037

摘要： A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.

摘要翻译： 基于开关键控调制方式的接收脉冲信号由频率为传输速率的二分之一的时钟信号操作的AD转换部分交替采样。 在同步中，采样定时调整部分中的延迟量彼此不同，从而对符号脉冲中两个不同点的相位进行采样。 根据采样值的比较结果调整可变延迟部分的延迟量，从而实现同步。 在解调时，保持可变延迟部分中的延迟量，并将采样定时调整部分中的延迟量切换到相同的值，并且对符号脉冲进行交替采样。 对采样值进行阈值判定，对判定结果进行并行到串行转换，从而得到解调输出。

公开(公告)号：US5839055A

公开(公告)日：1998-11-17

申请号：US538476

申请日：1995-10-03

申请人： Kazunari Higuchi ,  Terumi Hakamada ,  Kazuya Toki

发明人： Kazunari Higuchi ,  Terumi Hakamada ,  Kazuya Toki

IPC分类号： H04L27/26 ,  H04B1/66 ,  H04Q1/45 ,  H04B15/00 ,  H04B17/00

CPC分类号： H04L27/20 ,  H04B17/00 ,  H04L27/2626 ,  H04L27/2649

摘要： Between narrow band radio transmitting and receiving apparatuses, method and apparatus for shortening the starting failure time upon start of transmission are disclosed. By start of transmission at the transmission side, a DTMF signal at 697 Hz to 1633 Hz is outputted from a DTMF generator, and it is changed over to a DTMF signal at 1/10 frequency 0.02 sec later and outputted. A DTMF receiver at the reception side, when receiving a DTMF signal at 697 Hz to 1633 Hz, cancels the output mute circuit to set in service state. The DTMF receiver, when no longer receiving DTMF signal as a result of changeover to DTMF signal at 1/10 frequency, waits for an ordinary DTMF signal at 1/10 frequency, and cancels the output mute circuit until the end of transmission after reception thereof.

摘要翻译： 在窄带无线电发射和接收装置之间，公开了用于缩短发射开始时的起动失败时间的方法和装置。 通过发送侧的发送开始，从DTMF发生器输出697Hz〜1633Hz的DTMF信号，并在+ E变换为DTMF信号，频率为1/10 + EE频率0.02秒后输出 。 接收端的DTMF接收机在接收到697Hz至1633Hz的DTMF信号时，取消输出静音电路设置为运行状态。 DTMF接收机由于在+ E切换为DTMF信号而不再接收DTMF信号，为1/10 + EE频率，在+ E，1/10 + EE频率等待普通DTMF信号，并取消 输出静音电路，直到接收后发送结束。

公开(公告)号：US07496063B2

公开(公告)日：2009-02-24

申请号：US09879077

申请日：2001-06-13

申请人： Kazuya Toki ,  Shohei Taniguchi

发明人： Kazuya Toki ,  Shohei Taniguchi

IPC分类号： H04B7/185

CPC分类号： H04W52/16 ,  H03F1/32 ,  H03G3/3047 ,  H04B1/0475 ,  H04B17/354 ,  H04B2001/0416 ,  H04W52/24

摘要： A time-division multiplexing radio system controls transmission power based on an adjacent-channel leakage power ratio with precision and stability. The system has a directional coupler arranged at an output stage of a power amplifier in a transmitter and that has outputs directed to an antenna and a receiver, and a reception RF switch arranged at an input stage of a frequency converter in a receiver and that has inputs directed to the antenna and the coupler. Under transmission, the switch is switched over to the coupler so that the receiver receives the present channel to detect transmission power thereof. Also the receiver is set to receive an adjacent channel under transmission, so that adjacent-channel leakage power is detected. Based on those pieces of detected information, the ratio is calculated. To make the power ratio meet a specified condition, the transmission power of the transmitter is controlled.

摘要翻译： 时分复用无线电系统以精确和稳定的方式控制基于相邻信道泄漏功率比的传输功率。 该系统具有布置在发射机中的功率放大器的输出级的定向耦合器，并且具有定向到天线和接收器的输出以及布置在接收器中的变频器的输入级的接收RF开关，并且具有 输入到天线和耦合器。 在传输下，开关切换到耦合器，使得接收器接收当前信道以检测其发射功率。 此外，接收机被设置为接收传输下的相邻信道，从而检测相邻信道泄漏功率。 基于这些检测到的信息，计算该比率。 为了使功率比达到规定的条件，控制发射机的发射功率。

公开(公告)号：US08755468B2

公开(公告)日：2014-06-17

申请号：US12374737

申请日：2007-07-27

申请人： Michiaki Matsuo ,  Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki

发明人： Michiaki Matsuo ,  Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki

IPC分类号： H04L27/06

CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/0812 ,  H04B1/717 ,  H04B1/7183 ,  H04L7/0037

摘要： A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.

摘要翻译： 基于开关键控调制方式的接收脉冲信号由频率为传输速率的二分之一的时钟信号操作的AD转换部分交替采样。 在同步中，采样定时调整部分中的延迟量彼此不同，从而对符号脉冲中两个不同点的相位进行采样。 根据采样值的比较结果调整可变延迟部分的延迟量，从而实现同步。 在解调时，保持可变延迟部分中的延迟量，并将采样定时调整部分中的延迟量切换到相同的值，并且对符号脉冲进行交替采样。 对采样值进行阈值判定，对判定结果进行并行到串行转换，从而得到解调输出。

公开(公告)号：US07898312B2

公开(公告)日：2011-03-01

申请号：US12376024

申请日：2007-08-07

申请人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

发明人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00058

摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

摘要翻译： 本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。 本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号 ，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。

公开(公告)号：US20090315605A1

公开(公告)日：2009-12-24

申请号：US12376024

申请日：2007-08-07

申请人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

发明人： Hideki Aoyagi ,  Hitoshi Asano ,  Kazuya Toki ,  Michiaki Matsuo ,  Suguru Fujita

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00058

摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

摘要翻译： 本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。 本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号 ，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。