公开(公告)号：US20120319212A1

公开(公告)日：2012-12-20

申请号：US13598093

申请日：2012-08-29

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088

CPC分类号： H01L27/11 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/785

摘要： A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.

摘要翻译： 静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。 弯曲的翅片具有平行于直翅片的第一部分和第二部分。 弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。 下拉晶体管包括比传输栅极晶体管更多的鳍片。

公开(公告)号：US08120094B2

公开(公告)日：2012-02-21

申请号：US11838666

申请日：2007-08-14

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.

摘要翻译： 浅沟槽隔离（STI）结构具有在从基板表面的方向上从宽到窄的宽度从第一部分的顶部处的第一宽度到第一部分的底部处的第二宽度的顶部部分。 STI结构还包括在顶部下方的底部，其从顶部的底部膨胀到具有第三宽度的基本上加宽的横向距离。 通常，第三宽度基本上大于第二宽度。 本发明的STI结构可以提供期望的隔离特性，具有显着减小的纵横比，因此适用于先进加工技术中的器件隔离。

公开(公告)号：US20110133285A1

公开(公告)日：2011-06-09

申请号：US12890132

申请日：2010-09-24

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/785

摘要： A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.

摘要翻译： 静态随机存取存储器（SRAM）单元包括与直翅片物理断开的直翅片和弯曲的翅片。 弯曲的翅片具有平行于直翅片的第一部分和第二部分。 弯曲翅片的第一部分和直翅片之间的距离小于弯曲翅片的第二部分和直翅片之间的距离。 SRAM单元包括下拉晶体管，其包括第一栅极条的一部分，其分别与直鳍和弯曲鳍的第一部分形成第一和第二子下拉晶体管。 SRAM单元还包括一个包括第二栅极条的一部分的通过栅极晶体管，其形成具有直的鳍的第一子栅极晶体管。 下拉晶体管包括比传输栅极晶体管更多的鳍片。

公开(公告)号：US20110068413A1

公开(公告)日：2011-03-24

申请号：US12829084

申请日：2010-07-01

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： Circuits and methods for providing a dual gate oxide (DGO) embedded SRAM with additional logic portions, where the logic and the embedded SRAM have NMOS transistors having a common gate dielectric thickness but have different lightly doped drain (LDD) implantations formed using different LDD masks to provide optimum transistor operation. In an embodiment, a first embedded SRAM is a single port device and a second embedded SRAM is a dual port device having a separate read port. In certain embodiments, the second SRAM includes NMOS transistors having LDD implants formed using the logic portion LDD mask. Transistors formed with the logic portion LDD mask are faster and have lower Vt than transistors formed using a SRAM LDD mask. Dual core devices having multiple embedded SRAM arrays are disclosed. Methods for making the embedded SRAM are also disclosed.

摘要翻译： 用于提供具有附加逻辑部分的双栅极氧化物（DGO）嵌入式SRAM的电路和方法，其中逻辑和嵌入式SRAM具有NMOS晶体管，其具有共同的栅极电介质厚度，但具有不同的LDD掩模形成的轻掺杂漏极（LDD）注入 以提供最佳的晶体管操作。 在一个实施例中，第一嵌入式SRAM是单端口设备，第二嵌入式SRAM是具有单独读取端口的双端口设备。 在某些实施例中，第二SRAM包括具有使用逻辑部分LDD掩模形成的LDD注入的NMOS晶体管。 与逻辑部分LDD掩模形成的晶体管比使用SRAM LDD掩模形成的晶体管更快，具有更低的Vt。 公开了具有多个嵌入式SRAM阵列的双核心器件。 还公开了制造嵌入式SRAM的方法。

公开(公告)号：US07906389B2

公开(公告)日：2011-03-15

申请号：US12510951

申请日：2009-07-28

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/00

CPC分类号： H01L29/41766 ,  H01L21/28531 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region.

摘要翻译： 形成电连接电压节点和阱区的源极接触的对接接触结构及其形成方法，所述对接触点结构包括具有邻近半导体衬底上的电隔离区设置的阱区的有源区; MOSFET器件，其在有源区域上包括源区和漏区; 以及具有形成于所述源极区的第一部分和通过所述电隔离区形成到所述掺杂阱区的第二部分的导电接触。

公开(公告)号：US07812407B2

公开(公告)日：2010-10-12

申请号：US12697490

申请日：2010-02-01

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/108 ,  H01L27/11 ,  H01L27/112

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.

摘要翻译： 提供具有一排捆扎单元的存储器阵列。 根据本发明的实施例，捆扎单元位于两行存储器阵列之间。 捆扎单元在列中的两个存储单元的N +有效区之间提供P +带，并在存储器阵列的列中的两个存储单元的P +有效区之间提供N +带。 带状单元在存储器阵列的两行之间提供绝缘结构，并且创建存储器单元的更均匀的操作，而不管存储器阵列内的存储器单元的位置如何。 在一个实施例中，可以沿着垂直于捆扎单元行的方向沿着存储器阵列的外边缘形成虚拟N阱。 此外，可以在捆扎单元中形成晶体管，以在带状存储单元之间提供额外的绝缘。

公开(公告)号：US07812400B2

公开(公告)日：2010-10-12

申请号：US11725404

申请日：2007-03-19

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L23/48

CPC分类号： H01L21/823871 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823842

摘要： A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the first and the second well regions; and a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions.

摘要翻译： 提供具有减小的互扩散的半导体结构。 半导体结构包括半导体衬底; 半导体衬底中的第一阱区; 半导体衬底中的第二阱区; 在所述第一和第二阱区之间并邻接所述第一和第二阱区之间的绝缘区域; 在第一和第二阱区上的栅介质层; 以及栅极电极上的栅电极条，并从第一阱区上方延伸到第二阱区上方。 栅电极条包括第一阱区上的第一部分，第二阱区上的第二部分，以及绝缘区上的第三部分。 第三部分的厚度基本上小于第一部分和第二部分的厚度。

公开(公告)号：US07649226B2

公开(公告)日：2010-01-19

申请号：US11702807

申请日：2007-02-06

申请人： Jhon-Jhy Liaw ,  Mu-Chi Chiang

发明人： Jhon-Jhy Liaw ,  Mu-Chi Chiang

IPC分类号： H01L23/62

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/665

摘要： A semiconductor structure includes a semiconductor substrate; a first gate dielectric on the semiconductor substrate; a first gate electrode over the first gate dielectric; a first lightly doped source or drain (LDD) region in the semiconductor substrate and adjacent the first gate dielectric, wherein the first LDD region comprises arsenic; and a first deep source/drain region in the semiconductor substrate and adjacent the first gate dielectric. The first deep source/drain region comprises phosphorous, and a first phosphorous junction depth in the first deep source/drain region is greater than about three times a first arsenic junction depth in the first deep source/drain region.

摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上方的第一栅电极; 在所述半导体衬底中并与所述第一栅极电介质相邻的第一轻掺杂源极或漏极（LDD）区域，其中所述第一LDD区域包括砷; 以及半导体衬底中与第一栅极电介质相邻的第一深源极/漏极区。 第一深源极/漏极区域包括磷，并且第一深源极/漏极区域中的第一磷结深度大于第一深源极/漏极区域中的第一砷结深度的约三倍。

公开(公告)号：US20090286395A1

公开(公告)日：2009-11-19

申请号：US12510951

申请日：2009-07-28

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/768

CPC分类号： H01L29/41766 ,  H01L21/28531 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region.

摘要翻译： 形成电连接电压节点和阱区的源极接触的对接接触结构及其形成方法，所述对接触点结构包括具有邻近半导体衬底上的电隔离区设置的阱区的有源区; MOSFET器件，其在有源区域上包括源区和漏区; 以及具有形成于所述源极区的第一部分和通过所述电隔离区形成到所述掺杂阱区的第二部分的导电接触。

公开(公告)号：US20090014796A1

公开(公告)日：2009-01-15

申请号：US11775039

申请日：2007-07-09

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/01 ,  H01L21/84 ,  H01L29/94

CPC分类号： H01L27/088 ,  H01L21/32115 ,  H01L21/768 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.

摘要翻译： 接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在连接到MOS晶体管的栅极区域或第一接触点的第二介电层中的第二接触。 邻接源极/漏极区域和栅电极的对接接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在第二电介质层中的第二接触，其一端静止 在栅电极上，另一端与第一触点接触。