公开(公告)号：US08199567B2

公开(公告)日：2012-06-12

申请号：US13084906

申请日：2011-04-12

申请人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

发明人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

IPC分类号： G11C11/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

公开(公告)号：US07804703B2

公开(公告)日：2010-09-28

申请号：US12120583

申请日：2008-05-14

申请人： Dae-Won Ha ,  Gi-Tae Jeong

发明人： Dae-Won Ha ,  Gi-Tae Jeong

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

摘要翻译： 相变存储器件包括沿着半导体衬底上的方向延伸的字线。 低浓度半导体图案设置在字线上。 节点电极设置在低浓度半导体图案上。 肖特基二极管设置在低浓度半导体图案和节点电极之间。 相变电阻器设置在节点电极上。

公开(公告)号：US20080266942A1

公开(公告)日：2008-10-30

申请号：US12079869

申请日：2008-03-28

申请人： Chang-Wook Jeong ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

发明人： Chang-Wook Jeong ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

公开(公告)号：US20090201721A1

公开(公告)日：2009-08-13

申请号：US12320963

申请日：2009-02-10

申请人： Dae-Won Ha ,  Jung-Huyk Lee ,  Gi-Tae Jeong ,  Hyeong-Jun Kim

发明人： Dae-Won Ha ,  Jung-Huyk Lee ,  Gi-Tae Jeong ,  Hyeong-Jun Kim

IPC分类号： G11C11/00 ,  G11C11/416 ,  G11C5/14

CPC分类号： G11C13/0069 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0033 ,  G11C14/00 ,  G11C16/3431 ,  G11C29/028 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

摘要翻译： 相变存储器件及其写入方法允许在相变存储器件上写入易失性和非易失性数据。 可以通过将写入模式设置为易失性写入模式和非易失性写入模式之一来写入相变存储器件，并且通过施加与写入模式对应的写入脉冲将数据写入作为易失性或非易失性， 当不向相变存储器件供电时，保持非易失性数据并且不保留易失性数据。

公开(公告)号：US6066556A

公开(公告)日：2000-05-23

申请号：US184918

申请日：1998-11-02

申请人： Gi-Tae Jeong

发明人： Gi-Tae Jeong

IPC分类号： H01L21/8242 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76804 ,  H01L21/76877

摘要： Conductive lines are fabricated in integrated circuits by forming a groove in an insulating layer in the integrated circuit, wherein the groove has a sidewall, a base, and an upper surface. An insulating spacer is formed on the sidewall of the groove. The insulating spacer has a sloped contour from the sidewall to the base of the groove, defining a region at the base of the groove that is free of the insulating spacer. A conductive material is formed in the groove extending from the base of the groove to beneath the upper surface of the groove. The sloped contour of the spacer may provide for improved capping of conductive lines by allowing an increase in the amount of conductive material removed by a back-etching process, thereby reducing the likelihood of an electrical short between conductive lines.

摘要翻译： 导电线通过在集成电路中的绝缘层中形成沟槽而在集成电路中制造，其中沟槽具有侧壁，底座和上表面。 绝缘垫片形成在槽的侧壁上。 绝缘间隔物从侧壁到凹槽的基部具有倾斜的轮廓，在凹槽的底部限定一个没有绝缘间隔物的区域。 导电材料形成在从凹槽的基部延伸到槽的上表面的凹槽中。 通过允许通过背蚀刻工艺去除的导电材料的量的增加，间隔物的倾斜轮廓可以提供导电线的改进的覆盖，由此降低导电线之间的电短路的可能性。

公开(公告)号：US07940552B2

公开(公告)日：2011-05-10

申请号：US12079869

申请日：2008-03-28

申请人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

发明人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

IPC分类号： G11C11/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

公开(公告)号：US07830705B2

公开(公告)日：2010-11-09

申请号：US12216534

申请日：2008-07-07

申请人： Gi-Tae Jeong

发明人： Gi-Tae Jeong

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0054

摘要： Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively different resistance states among the resistance states each time the main cells are programmed, and a reference voltage generation circuit sensing the reference cells to generate reference voltages for identifying each of the resistance states.

摘要翻译： 提供了一种相变存储器件及其读取方法。 相变存储器件的示例实施例可以包括被编程为具有分别对应于多位数据的多个电阻状态中的任何一个的主单元，被编程为每次具有至少两个电阻状态之间的不同电阻状态的参考单元 主单元被编程，以及参考电压产生电路感测参考单元以产生用于识别每个电阻状态的参考电压。

公开(公告)号：US20090016100A1

公开(公告)日：2009-01-15

申请号：US12216534

申请日：2008-07-07

申请人： Gi-Tae Jeong

发明人： Gi-Tae Jeong

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0054

摘要： Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively different resistance states among the resistance states each time the main cells are programmed, and a reference voltage generation circuit sensing the reference cells to generate reference voltages for identifying each of the resistance states.

摘要翻译： 提供了一种相变存储器件及其读取方法。 相变存储器件的示例实施例可以包括被编程为具有分别对应于多位数据的多个电阻状态中的任何一个的主单元，被编程为每次具有至少两个电阻状态之间的不同电阻状态的参考单元 主单元被编程，以及参考电压产生电路感测参考单元以产生用于识别每个电阻状态的参考电压。

公开(公告)号：US08050083B2

公开(公告)日：2011-11-01

申请号：US12320963

申请日：2009-02-10

申请人： Dae-Won Ha ,  Jung-Hyuk Lee ,  Gi-Tae Jeong ,  Hyeong-Jun Kim

发明人： Dae-Won Ha ,  Jung-Hyuk Lee ,  Gi-Tae Jeong ,  Hyeong-Jun Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0033 ,  G11C14/00 ,  G11C16/3431 ,  G11C29/028 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

摘要翻译： 相变存储器件及其写入方法允许在相变存储器件上写入易失性和非易失性数据。 可以通过将写入模式设置为易失性写入模式和非易失性写入模式之一来写入相变存储器件，并且通过施加与写入模式对应的写入脉冲将数据写入作为易失性或非易失性， 当不向相变存储器件供电时，保持非易失性数据并且不保留易失性数据。

公开(公告)号：US20110188304A1

公开(公告)日：2011-08-04

申请号：US13084906

申请日：2011-04-12

申请人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

发明人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

IPC分类号： G11C11/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。