公开(公告)号：US10559261B2

公开(公告)日：2020-02-11

申请号：US16155422

申请日：2018-10-09

Applicant: LG Display Co., Ltd.

Inventor： Sungwook Chang ,  Juhnsuk Yoo ,  Jungchul Kim ,  Sungwook Yoon ,  Hoyoung Ko

IPC: G09G3/3258 ,  G09G3/3233 ,  H01L27/32

Abstract: An electroluminescent display is disclosed. An electroluminescent display comprises a display panel including a plurality of pixels, each of the plurality of pixels including subpixels. A pixel circuit of each subpixels includes a driving transistor configured to drive the electroluminescent diode, a first switching transistor configured to supply a first voltage to a gate of the driving transistor in response to a first scan signal, a second switching transistor configured to supply a second voltage to the gate of the driving transistor in response to a second scan signal, a third switching transistor configured to supply the second voltage to a first electrode of the driving transistor in response to the second scan signal, a fourth switching transistor configured to supply a first supply voltage to a second electrode of the driving transistor in response to an emission control signal, a first capacitor between a first node connected to the gate electrode of the driving transistor and a second node connected to the second electrode of the driving transistor, and a second capacitor between the second node and a power supply line supplied with the second voltage or the first supply voltage.

公开(公告)号：US09824771B2

公开(公告)日：2017-11-21

申请号：US14133243

申请日：2013-12-18

Applicant: LG DISPLAY CO., LTD.

Inventor： Sunghyun Cho ,  Chungsik Kong ,  Sungwook Chang

IPC: G11C19/00 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.

公开(公告)号：US09774325B2

公开(公告)日：2017-09-26

申请号：US14969280

申请日：2015-12-15

Applicant: LG Display Co., Ltd.

Inventor： DongSoo Kim ,  Hun Jeoung ,  SangHee Yu ,  SungHyun Cho ,  BoSun Lee ,  Sungwook Chang

IPC: G09G3/36 ,  H03K17/687 ,  G09G3/3225 ,  G09G3/3266 ,  G11C19/28 ,  G06F1/04 ,  G09G3/20

CPC classification number: H03K17/6871 ,  G06F1/04 ,  G09G3/2092 ,  G09G3/3225 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.