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    Memory Architecture for Layered Low-Density Parity-Check Decoder
    13.
    发明申请
    Memory Architecture for Layered Low-Density Parity-Check Decoder 有权
    分层低密度奇偶校验解码器的内存架构

    公开(公告)号：US20140223259A1

    公开(公告)日：2014-08-07

    申请号：US13760609

    申请日：2013-02-06

    Applicant: LSI CORPORATION

    Inventor： Zongwang Li ,  Yang Han ,  Kaichi Zhang ,  Chung-Li Wang

    IPC: G06F11/10

    CPC classification number: G06F11/10 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2707 ,  H03M13/6505 ,  H03M13/6566

    Abstract: A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.

    Abstract translation: LE硬判决存储器包括用于交织来自第一和第二循环的L值的全局映射元素，并将交错值存储在第一存储器元件中。 然后，低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。

    System and method for check-node unit message processing
    16.
    发明授权
    System and method for check-node unit message processing 有权
    用于校验节点单元消息处理的系统和方法

    公开(公告)号：US09244685B2

    公开(公告)日：2016-01-26

    申请号：US13667450

    申请日：2012-11-02

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Chung-Li Wang ,  Kaitlyn T. Nguyen ,  Keklik Bayam Alptekin

    IPC: H03M13/00 ,  G06F9/30

    CPC classification number: G06F9/30145 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/616 ,  H03M13/6566

    Abstract: The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

    Abstract translation: 本公开涉及一种利用随机存取存储器（RAM）存储和处理校验节点单元（CNU）消息的系统和方法。 解码器包括CNU的分层阵列，其被配置为接收与解码器正在操作的至少一个数据段的解码比特相关联的至少一个可变节点单元（VNU）消息。 解码器还包括CNU消息转换器，其被配置为置换VNU消息的至少一个初始循环，以生成具有基于RAM的处理的子循环的转换的CNU消息。 解码器还包括RAM，其被配置为将转换的CNU消息的子循环存储在可寻址存储器块处以用于并行VNU处理。

    Low density parity check decoder with dynamic scaling
    17.
    发明授权
    Low density parity check decoder with dynamic scaling 有权
    低密度奇偶校验解码器，动态缩放

    公开(公告)号：US09130589B2

    公开(公告)日：2015-09-08

    申请号：US13777841

    申请日：2013-02-26

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Zongwang Li ,  Shaohua Yang ,  Chung-Li Wang ,  Fan Zhang

    IPC: G11B20/18 ,  H03M13/13 ,  H03M13/11 ,  H03M13/00 ,  H03M13/27

    CPC classification number: H03M13/1117 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1111 ,  H03M13/1171 ,  H03M13/27 ,  H03M13/6331 ,  H03M13/658

    Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

    Abstract translation: 公开了一种数据处理系统，包括具有可变节点处理器的低密度奇偶校验解码器，校验节点处理器和缩放器电路。 低密度奇偶校验解码器可用于在缩放器电路中缩放具有缩放因子的软信息，同时在可变节点处理器和变量节点中对可变节点消息进行迭代生成并处理校验节点，以校验校验节点处理器中的节点消息 多个检查节点和可变节点。 缩放因子是从低密度奇偶校验解码器的输入中的可能值的分布导出的。

    Systems and methods for multi-stage encoding of concatenated low density parity check codes
    18.
    发明授权
    Systems and methods for multi-stage encoding of concatenated low density parity check codes 有权
    连接低密度奇偶校验码的多级编码的系统和方法

    公开(公告)号：US09048873B2

    公开(公告)日：2015-06-02

    申请号：US13912079

    申请日：2013-06-06

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Yu Kou ,  Chung-Li Wang ,  Shaohua Yang ,  Shu Li

    IPC: H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1171 ,  H03M13/611 ,  H03M13/616

    Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

    Abstract translation: 数据编码系统包括数据编码器电路，其可操作以用低密度奇偶校验码矩阵的分量矩阵对多个数据扇区中的每一个进行编码，并产生输出码字。 数据编码器电路包括可用于计算和组合用于数据扇区的综合征的校正子计算电路。

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