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    Timing error detector with diversity loop detector decision feedback
    1.
    发明授权
    Timing error detector with diversity loop detector decision feedback 有权
    具有分集环路检测器判定反馈的定时误差检测器

    公开(公告)号：US09275655B2

    公开(公告)日：2016-03-01

    申请号：US13941464

    申请日：2013-07-13

    Applicant: LSI Corporation

    Inventor： Bruce Wilson ,  Yang Han ,  Yu Kou ,  Rui Cao

    IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10

    CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2516

    Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

    Abstract translation: 本公开的方面涉及用于检测定时误差的装置，包括模数转换器电路，分集环路检测器和定时误差计算电路。 模数转换器电路可操作以将输入信号转换为一系列数字采样。 分集环路检测器可操作以将数据检测算法应用于在不同相位偏移处从一系列数字样本导出的多个信号，以选择相位偏移中的一个，并产生具有所选相位偏移的检测输出。 定时误差计算电路可用于至少部分地基于所选择的相位偏移来计算模数转换器电路的定时误差。

    Systems and methods for multi-stage encoding of concatenated low density parity check codes
    3.
    发明授权
    Systems and methods for multi-stage encoding of concatenated low density parity check codes 有权
    连接低密度奇偶校验码的多级编码的系统和方法

    公开(公告)号：US09048873B2

    公开(公告)日：2015-06-02

    申请号：US13912079

    申请日：2013-06-06

    Applicant: LSI Corporation

    Inventor： Zongwang Li ,  Yu Kou ,  Chung-Li Wang ,  Shaohua Yang ,  Shu Li

    IPC: H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1171 ,  H03M13/611 ,  H03M13/616

    Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

    Abstract translation: 数据编码系统包括数据编码器电路，其可操作以用低密度奇偶校验码矩阵的分量矩阵对多个数据扇区中的每一个进行编码，并产生输出码字。 数据编码器电路包括可用于计算和组合用于数据扇区的综合征的校正子计算电路。

    Systems and methods for loop pulse estimation
    4.
    发明授权
    Systems and methods for loop pulse estimation 有权
    环路脉冲估计的系统和方法

    公开(公告)号：US08929010B1

    公开(公告)日：2015-01-06

    申请号：US14029559

    申请日：2013-09-17

    Applicant: LSI Corporation

    Inventor： Rui Cao ,  Yu Kou ,  Xuebin Wu ,  Yang Han

    IPC: G11B20/10 ,  G11B5/035 ,  H04L25/03

    CPC classification number: H04L25/03885 ,  G11B5/09 ,  G11B20/10027 ,  H04L25/0212 ,  H04L25/0238 ,  H04L25/025

    Abstract: A data processing system includes a digital data input operable to receive digital data, a digital data values input operable to receive values of the digital data, a loop pulse response estimation circuit operable to calculate a loop pulse response based on the digital data and the values of the digital data and based at least in part on past values of the loop pulse response, and a scaling circuit operable to scale the loop pulse response based at least in part on an absolute sum of the loop pulse response to yield a scaled loop pulse response.

    Abstract translation: 数据处理系统包括可操作以接收数字数据的数字数据输入，可操作以接收数字数据值的数字数据值输入;循环脉冲响应估计电路，其可操作以基于数字数据和值计算环路脉冲响应 至少部分地基于环路脉冲响应的过去值，以及缩放电路，其可操作以至少部分地基于环路脉冲响应的绝对和来缩放环路脉冲响应，以产生缩放的环路脉冲 响应。

    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS
    5.
    发明申请
    SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS 有权
    信号处理电路由分钟控制的FRONTEND和后端电路

    公开(公告)号：US20140181570A1

    公开(公告)日：2014-06-26

    申请号：US13724946

    申请日：2012-12-21

    Applicant: LSI CORPORATION

    Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

    IPC: G06F1/06

    CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

    Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

    Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

    Diversity loop detector with component detector switching
    6.
    发明授权
    Diversity loop detector with component detector switching 有权
    具有分量检测器切换的分集环路检测器

    公开(公告)号：US09407295B2

    公开(公告)日：2016-08-02

    申请号：US13741482

    申请日：2013-01-15

    Applicant: LSI Corporation

    Inventor： Yang Han ,  Yu Kou ,  Xuebin Wu ,  Bruce A. Wilson

    IPC: G06F17/18 ,  H03M13/41

    CPC classification number: H03M13/41

    Abstract: Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.

    Abstract translation: 本公开的方面涉及用于为分集环路检测器提供分量检测器切换的系统和方法。 通过周期状态似然重置处理，基于斜率的切换处理或交叉连接处理之一来执行分量检测器之间的切换。 联合决策电路在组件检测器之间切换，以通过存在恒定或过渡相位偏移来促进改进的性能。

    DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING
    9.
    发明申请
    DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING 有权
    多样性环路检测器与组件检测器切换

    公开(公告)号：US20140200849A1

    公开(公告)日：2014-07-17

    申请号：US13741482

    申请日：2013-01-15

    Applicant: LSI CORPORATION

    Inventor： Yang Han ,  Yu Kou ,  Xuebin Wu ,  Bruce A. Wilson

    IPC: G06F17/18

    CPC classification number: H03M13/41

    Abstract: Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.

    Abstract translation: 本公开的方面涉及用于为分集环路检测器提供分量检测器切换的系统和方法。 通过周期状态似然重置处理，基于斜率的切换处理或交叉连接处理之一来执行分量检测器之间的切换。 联合决策电路在组件检测器之间切换，以通过存在恒定或过渡相位偏移来促进改进的性能。

    Automatic On-Drive Sync-Mark Search and Threshold Adjustment
    10.
    发明申请
    Automatic On-Drive Sync-Mark Search and Threshold Adjustment 有权
    自动驱动器同步标记搜索和阈值调整

    公开(公告)号：US20140286149A1

    公开(公告)日：2014-09-25

    申请号：US13850942

    申请日：2013-03-26

    Applicant: LSI CORPORATION

    Inventor： Rui Cao ,  Haitao Xia ,  Yu Kou

    IPC: G11B27/30

    CPC classification number: G11B27/3027 ,  G11B20/10 ,  G11B20/1403 ,  G11B27/10

    Abstract: A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern.

    Abstract translation: 硬盘驱动器包括一个处理器，用于自动调整阈值水平以查找同步标记。 处理器确定特定图案长度的所有可能的同步标记图案，并参考真实世界数据分析每个图案。 使用距离最大的图案。 然后动态调整阈值电平，以产生给定模式的最低可能故障率。

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