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    Data processing system with adjacent track interference metric
    11.
    发明授权
    Data processing system with adjacent track interference metric 有权
    具有相邻轨道干扰度量的数据处理系统

    公开(公告)号：US08861109B1

    公开(公告)日：2014-10-14

    申请号：US13963589

    申请日：2013-08-09

    Applicant: LSI Corporation

    Inventor： Eui Seok Hwang ,  Richard Rauschmayer ,  Shaohua Yang ,  Bruce Wilson

    IPC: G11B27/36

    CPC classification number: G11B5/02 ,  G11B20/10305 ,  G11B20/10472

    Abstract: A data processing circuit includes a long magnet identification circuit operable to identify long magnet bits in data to be processed, the long magnet bits comprising bits having a same value as a number of preceding and subsequent bits, an error calculation circuit operable to subtract an ideal version of the long magnet bits from the long magnet bits to yield an error signal, an adjacent track interference metric calculation circuit operable to calculate an adjacent track interference metric based on the error signal, and a comparator circuit operable to compare the adjacent track interference metric with a threshold value and to assert a refresh signal when the adjacent track interference metric is greater than the threshold value.

    Abstract translation: 数据处理电路包括：长磁体识别电路，用于识别要处理的数据中的长磁头位;所述长磁头位包括与前一位和后续位数相同值的位;误差计算电路，用于减去理想 版本的长磁头位产生误差信号，相邻轨道干扰度量计算电路，可操作以基于误差信号计算相邻轨道干扰度量;以及比较器电路，可操作以比较相邻轨道干扰度量 并且当相邻轨道干扰度量大于阈值时，断言刷新信号。

    PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL
    12.
    发明申请
    PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL 有权
    可编程循环低密度奇偶校验（QC LDPC）编解码器

    公开(公告)号：US20130091403A1

    公开(公告)日：2013-04-11

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/05

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

    SERIAL PORT COMMUNICATION FOR STORAGE DEVICE USING SINGLE BIDIRECTIONAL SERIAL DATA LINE
    13.
    发明申请
    SERIAL PORT COMMUNICATION FOR STORAGE DEVICE USING SINGLE BIDIRECTIONAL SERIAL DATA LINE 有权
    使用单一双向串行数据线的存储设备的串行端口通信

    公开(公告)号：US20160012846A1

    公开(公告)日：2016-01-14

    申请号：US14329467

    申请日：2014-07-11

    Applicant: LSI Corporation

    Inventor： Ross S. Wilson ,  Daniel J. Dolan ,  David W. Kelly ,  Richard Rauschmayer

    IPC: G11B20/10 ,  G11B5/09

    CPC classification number: G11B20/10027 ,  G06F3/06 ,  G11B5/02 ,  G11B5/09 ,  G11B20/10222 ,  G11B2005/0021

    Abstract: A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

    Abstract translation: 提供了一种用于实现存储设备中的控制器与前置放大器之间的通信的方法。 例如，该方法包括实现串行端口，该串行端口被配置为通过单个双向串行数据线在控制器和前置放大器之间传输数字信号。 串行端口被控制以便在双向串行数据线上从控制器到前置放大器的第一方向或从前置放大器到控制器的第二方向选择性地发送数字信号。

    System and method for power saving modes in multi-sensor magnetic recording
    15.
    发明授权
    System and method for power saving modes in multi-sensor magnetic recording 有权
    多传感器磁记录中省电模式的系统和方法

    公开(公告)号：US09001446B1

    公开(公告)日：2015-04-07

    申请号：US14194069

    申请日：2014-02-28

    Applicant: LSI Corporation

    Inventor： Bruce A. Wilson ,  Richard Rauschmayer ,  Peter J. Windler ,  Jefferson E. Singleton ,  Shaohua Yang ,  Jeffrey P. Grundvig

    IPC: G11B5/09 ,  G11B5/596 ,  G11B20/10

    CPC classification number: G11B5/59616 ,  G11B5/09 ,  G11B19/00 ,  G11B20/10037 ,  G11B2005/0008

    Abstract: A system and method for power management in a hard disk drive (HDD) assembly incorporating two or more read sensors includes directing a read/write head to follow a track; depowering one or more read sensors and readpath circuits associated with the read sensors; reading an analog readback signal through the first read sensor; processing the signal through an analog front-end to generate an input signal; sampling the input signal through an analog to digital converter at a first frequency to generate a first sampling signal; sampling the input signal through a second analog to digital converter at a second frequency to generate a second sampling signal; and generating a digital output signal from either or both sampling signals at a third sampling frequency through a digital signal processor. The method may additionally comprise adjusting a sampling frequency when power level reaches a threshold.

    Abstract translation: 包含两个或更多个读取传感器的硬盘驱动器（HDD）组件中的电源管理的系统和方法包括引导读/写头跟随轨道; 降低与读取的传感器相关联的一个或多个读取传感器和读取路径电路; 通过第一个读取传感器读取模拟回读信号; 通过模拟前端处理信号以产生输入信号; 以第一频率通过模数转换器对输入信号进行采样，以产生第一采样信号; 以第二频率通过第二模数转换器对输入信号进行采样，以产生第二采样信号; 以及通过数字信号处理器以第三采样频率从一个或两个采样信号产生数字输出信号。 该方法还可以包括当功率电平达到阈值时调整采样频率。

    Touchdown detection in magnetic disk storage devices
    16.
    发明授权
    Touchdown detection in magnetic disk storage devices 有权
    触摸屏检测在磁盘存储设备中

    公开(公告)号：US08873194B1

    公开(公告)日：2014-10-28

    申请号：US14242633

    申请日：2014-04-01

    Applicant: LSI Corporation

    Inventor： Xiufeng Song ,  Richard Rauschmayer

    IPC: G11B21/02

    CPC classification number: G11B5/6076 ,  G11B5/6029

    Abstract: Touchdown detection in magnetic storage devices is provided to detect contact between a storage medium and a magnetic head having an embedded contact sensor. A sample stream is obtained, which includes samples of a sensor signal output from the embedded contact sensor. The sample stream is segmented into multiple segments. A modulation depth is determined for each of the segments. A combined modulation depth is determined by combining the modulation depths of the segments using a weighting function. The combined modulation depth is compared with a threshold. A determination is made as to whether the magnetic head makes contact with the storage medium based on a result of the comparing.

    Abstract translation: 提供磁存储装置中的触地屏检测用于检测存储介质和具有嵌入式触点传感器的磁头之间的接触。 获得样品流，其包括从嵌入式接触传感器输出的传感器信号的样品。 样本流被分段成多个段。 确定每个段的调制深度。 通过使用加权函数组合段的调制深度来确定组合调制深度。 将组合的调制深度与阈值进行比较。 基于比较的结果，确定磁头是否与存储介质接触。

    Systems and methods for sync mark based read offset detection
    17.
    发明授权
    Systems and methods for sync mark based read offset detection 有权
    基于同步标记的读取偏移检测的系统和方法

    公开(公告)号：US08861122B1

    公开(公告)日：2014-10-14

    申请号：US14108282

    申请日：2013-12-16

    Applicant: LSI Corporation

    Inventor： Eui Seok Hwang ,  Richard Rauschmayer

    IPC: G11B5/596

    CPC classification number: G11B5/59616 ,  G11B5/59627

    Abstract: A data processing system includes a cross-correlation calculator operable to calculate cross-correlations between an input signal and each of three different sync patterns associated with a target track and neighboring tracks, a detector operable to select a largest of the cross-correlations, a threshold comparator operable to compare the cross-correlations with a threshold to determine a direction of any position error of a read head, and a position error estimator operable to estimate a position error of the read head based at least in part on the cross-correlations.

    Abstract translation: 数据处理系统包括互相关计算器，其可操作以计算输入信号与与目标轨道和相邻轨道相关联的三个不同同步模式中的每一个之间的互相关，可操作以选择最大的交叉相关的检测器 阈值比较器，其可操作以将交叉相关与阈值进行比较，以确定读取头的任何位置误差的方向;以及位置误差估计器，其可操作以至少部分地基于互相关来估计读取头的位置误差 。

    MULTIPLEXED COMMUNICATION IN A STORAGE DEVICE
    18.
    发明申请
    MULTIPLEXED COMMUNICATION IN A STORAGE DEVICE 有权
    存储设备中的多路通讯

    公开(公告)号：US20150318014A1

    公开(公告)日：2015-11-05

    申请号：US14267354

    申请日：2014-05-01

    Applicant: LSI Corporation

    Inventor： Ross S. Wilson ,  David W. Kelly ,  Daniel J. Dolan ,  Richard Rauschmayer

    IPC: G11B20/10

    CPC classification number: G11B20/10027 ,  G06F3/06 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/10018 ,  G11B20/10222 ,  G11B2005/0021

    Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

    Abstract translation: 提供了一种方法，例如在存储设备中的记录通道和前置放大器之间的模拟总线上实现复用通信。 记录通道内的读数据电路的第一输入可切换地连接到模拟总线的第一模拟线，以便在读操作期间通过第一模拟线接收从前置放大器发送到记录通道的读数据。 此外，记录通道内的写入数据电路的写入数据输出可切换地连接到模拟总线的第一模拟线，以在写入操作期间通过第一模拟线将写入数据从记录通道传送到前置放大器。

    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    19.
    发明授权
    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
    用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器

    公开(公告)号：US09166622B2

    公开(公告)日：2015-10-20

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/00 ,  H03M13/05 ,  H03M13/11 ,  G06F11/10 ,  H03M13/27

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

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