公开(公告)号：US08923371B2

公开(公告)日：2014-12-30

申请号：US13729405

申请日：2012-12-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/38 ,  H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US08848769B2

公开(公告)日：2014-09-30

申请号：US13647502

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Mohammad Mobin ,  Vladimir Sindalovsky ,  Amaresh Malipatil ,  Thomas F. Gibbons, Jr. ,  Ye Liu ,  Lane A. Smith

IPC: H04B1/38 ,  H04L5/16 ,  H04B1/40

CPC classification number: H04B1/40 ,  H04L25/03343 ,  H04L25/03885

Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.

Abstract translation: 本发明的实施例允许在联合发射机（TX）和接收机（RX）均衡期间调整发射机幅度。 在联合TX和RX适配期间，当接收机需要增益更新时，接收机增益更新被屏蔽在高于或低于预设范围。 RX增益更新（指令）被编码成通过背信道通信传送的发送机幅度更新（指令）。 在RX增益达到指定范围后，RX增益转换为TX幅度更新。 这种屏蔽，编码和转换保留了一定量的RX增益范围，以解决随着时间的过程，电压和温度（PVT）变化引起的RX增益变化，并且还在受限的VGA带宽上在接收机中提供更好的线性均衡。

公开(公告)号：US08803573B2

公开(公告)日：2014-08-12

申请号：US13647470

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Joseph Anidjar ,  Lane A. Smith ,  Brett David Hardy

IPC: H03L7/06

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/1075 ,  H03L7/146 ,  H03L2207/06

Abstract: In described embodiments, a VCO based CDR for a SerDes device includes a phase detector, a VCO responsive to a first control signal and a second control signal and generating an output signal, a frequency calibration module configured to calibrate the frequency of the output signal by performing a coarse calibration and a subsequent fine calibration, a gear shifting control module controlling a gain change of the first and second control signals in time, and a look-up table created by fine calibration values generated from the frequency calibration module, wherein the programmed variable gain of the gear shifting control module is calculated by a calculation circuit employing the fine calibration values stored in the look-up table, the calculation of the calculation circuit adjusts gear shifting down, and adjusts a gear shifting gain, and adjusting an overall CDR gain over a VCO control curve.

Abstract translation: 在所描述的实施例中，用于SerDes设备的基于VCO的CDR包括相位检测器，响应于第一控制信号的VCO和第二控制信号，并产生输出信号;频率校准模块，被配置为通过以下步骤校准输出信号的频率 执行粗略校准和随后的精细校准，齿轮控制模块及时控制第一和第二控制信号的增益变化，以及通过由频率校准模块产生的精细校准值产生的查找表，其中编程 通过采用存储在查表中的精细校准值的计算电路来计算变速控制模块的可变增益，计算电路的计算调节换档增益，并且调整换档增益，并且调整总体CDR 增益超过VCO控制曲线。

公开(公告)号：US20140185658A1

公开(公告)日：2014-07-03

申请号：US13729405

申请日：2012-12-28

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US20140098844A1

公开(公告)日：2014-04-10

申请号：US13647502

申请日：2012-10-09

Applicant: LSI Corporation

Inventor： Mohammad Mobin ,  Vladimir Sindalovsky ,  Amaresh Malipatil ,  Thomas F. Gibbons, JR. ,  Ye Liu ,  Lane A. Smith

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H04L25/03343 ,  H04L25/03885

Abstract: Embodiments of the present invention allow for adjustment of transmitter amplitude during joint transmitter (TX) and receiver (RX) equalization. During joint TX and RX adaptation, when the receiver requires a gain update, the receiver gain update is masked above or below a preset range. The RX gain update (instruction) is encoded into a transmitter amplitude update (instruction) transferred through back channel communication. The translation of RX gain to TX amplitude update is performed after the RX gain reaches a specified range. Such masking, encoding and translation reserves a certain amount RX gain range to account for RX gain variation due to process, voltage, and temperature (PVT) changes over time, and also to offer better linear equalization in the receiver over a constrained VGA bandwidth.

Abstract translation: 本发明的实施例允许在联合发射机（TX）和接收机（RX）均衡期间调整发射机幅度。 在联合TX和RX适配期间，当接收机需要增益更新时，接收机增益更新被屏蔽在高于或低于预设范围。 RX增益更新（指令）被编码成通过背信道通信传送的发送机幅度更新（指令）。 在RX增益达到指定范围后，RX增益转换为TX幅度更新。 这种屏蔽，编码和转换保留了一定量的RX增益范围，以解决随着时间的过程，电压和温度（PVT）变化引起的RX增益变化，并且还在受限的VGA带宽上在接收机中提供更好的线性均衡。