公开(公告)号：US20160142233A1

公开(公告)日：2016-05-19

申请号：US14541345

申请日：2014-11-14

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Brett D. Hardy

IPC: H04L27/01 ,  H04L7/00

CPC classification number: H04L7/0079 ,  H03G3/3078 ,  H04L25/0298 ,  H04L25/03878

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.

Abstract translation: 描述的实施例在SerDes设备中提供了一种通过基于过程，电压，温度（PVT）和数据速率变化的可编程偏置来调整数据路径增益的自适应过程。 这种适应过程扩展了偏置电流动态范围，低频增益可编程为任何PVT和数据速率角下的给定可变增益放大器（VGA）设置的期望目标值范围。 接收（RX）数据路径结构通过基于感测的PVT和数据速率变化的可编程偏置来自适应数据路径增益。 低频衰减/增益范围扩展，并且可以通过在任何给定的PVT和数据速率条件下的给定VGA和线性均衡器（LEQ）设置的SerDes设备RX自适应处理来编程到期望的目标范围。

公开(公告)号：US20150256364A1

公开(公告)日：2015-09-10

申请号：US14248624

申请日：2014-04-09

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Vladimir Sindalovsky

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/03808

Abstract: Described embodiments provide for de-coupling between adaptation of decision feedback equalizer (DFE) filter taps and transmitter (TX) post cursor filtering in group delay (GD)-based adaptation. Consequently, an excessive build-up of transmitter post cursor effects and its excessive equalization cancellation by the DFE may be substantially reduced or eliminated. By breaking this coupling, a transmitter does not over equalize a signal, the DFE does not attempt to “undo” the over equalization, and a variable gain amplifier (VGA) in the receiver front end data path generally does not apply gain to amplify the signal back again due to the reduced DC level. GD-based TX post cursor adaptation may reduce over equalization effect and hence save power and increase performance by not over equalizing the signal.

Abstract translation: 描述的实施例提供了在基于组延迟（GD）的适配中的决策反馈均衡器（DFE）滤波器抽头和发射器（TX））后光标滤波的适配之间的去耦合。 因此，可以显着地减少或消除发射机后光标效应的过度建立及其由DFE的过度均衡消除。 通过断开该耦合，发射机不会使信号过度均衡，DFE不会尝试“撤消”过均衡，并且接收机前端数据通道中的可变增益放大器（VGA）通常不适用增益放大 由于降低的直流电平，再次发出信号。 基于GD的TX后光标自适应可以减少均衡效应，从而通过不使信号过度均衡来节省功率并提高性能。

公开(公告)号：US09025655B1

公开(公告)日：2015-05-05

申请号：US14072895

申请日：2013-11-06

Applicant: LSI Corporation

Inventor： Rajesh Ramadoss ,  Mohammad S. Mobin ,  Thomas F. Gibbons, Jr.

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03057 ,  H04L25/03343

Abstract: A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the DFE. The post-cursor tap weight of the transmitter filter is adjusted up or down based on a comparison of the gain coefficient to a set. of limits. The post-cursor tap weight is transmitted to the transmitter over a reverse channel and then equalizers in the receiver readapt. Alternatively, eye opening data and a DFE tap coefficient are used to determine whether the post-cursor tap weight is adjusted up or down.

Abstract translation: 一种在高速数字数据传输系统中调整发射机FIR滤波器中的后光标抽头权重的方法。 接收机通过前向信道接收来自发射机的信号，并使用耦合到前向信道的自适应模拟均衡器和耦合到模拟均衡器的判决反馈均衡器（DFE）来均衡接收信号。 用于通过模拟均衡器调节峰值的增益系数使用DFE产生的误差信号进行调整。 基于增益系数与一组的比较，发送器滤波器的后置光标重量被上下调整。 的限制。 后置光标抽头权重通过反向通道发送到发送器，然后在接收器中对其进行均衡。 或者，使用眼睛打开数据和DFE抽头系数来确定是否向上或向下调整后光标抽头重量。

公开(公告)号：US08923371B2

公开(公告)日：2014-12-30

申请号：US13729405

申请日：2012-12-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/38 ,  H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US20140185658A1

公开(公告)日：2014-07-03

申请号：US13729405

申请日：2012-12-28

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Mohammad S. Mobin

IPC: H04B1/40

CPC classification number: H04B1/40 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0058 ,  H04L7/0337

Abstract: A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

Abstract translation: 一个SerDes数据采样控制器，其包括一个换档数据采样时钟，该数据采样时钟在CDR相位锁定阶段期间将单位间隔中心处的数据采样偏差置零，然后将数据采样定时从该单位间隔的中心偏离为 DFE系数在数据传输阶段适应。 这允许控制器在CDR相位锁定阶段期间实现最佳（非限制）数据采样定时，然后在DFE系数适应于在期间为数据位采样提供最佳（偏斜））数据采样定时之前扭曲数据采样定时 数据传输阶段。 数据采样齿轮换档器可以向从同相（I）数据采样时钟差分改变正交（Q）转换采样时钟的转换采样或正交（Q）数据采样时钟施加可变偏移值。

公开(公告)号：US09325537B2

公开(公告)日：2016-04-26

申请号：US14244474

申请日：2014-04-03

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Chintan M. Desai ,  Freeman Y. Zhong ,  Ye Liu

IPC: H04L27/08 ,  H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/06

Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

Abstract translation: 在所描述的实施例中，串行器/解串器（SerDes）器件中的处理，电压，温度（PVT）补偿采用并入SerDes接收器适配过程的闭环适配补偿。 在实施闭环可变增益放大器适配时，其中监视适应的判决反馈均衡器（DFE）目标电平（例如，抽头H0）的检测方法采用该DFE目标电平。 DFE目标水平与VGA电平一起用于控制PVT设置，以通过检测一个电压转角条件来维持目标SerDes数据通路增益。 检测到的PVT拐角条件用于产生控制信号，以进一步调整根据PVT条件所要求的LEQ和DFE数据路径差分对增益。

公开(公告)号：US20150263848A1

公开(公告)日：2015-09-17

申请号：US14257315

申请日：2014-04-21

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Chintan M. Desai ,  Ye Liu

IPC: H04L7/00 ,  H03L7/08

CPC classification number: H03L7/0807 ,  H04L7/0004 ,  H04L7/033

Abstract: Described embodiments provide for, in a clock and data recovery (CDR) circuit, detection of loss of acquisition and CDR restarting with corrective integral accumulator register seeding and gearshift restarting. In described embodiments, a mechanism is employed to cause faster loss of lock condition if the CDR circuit directed on an incorrect acquisition trajectory, actual loss of CDR lock is then detected, and CDR acquisition is recovered with corrective integral accumulator seeding.

Abstract translation: 描述的实施例在时钟和数据恢复（CDR）电路中提供使用校正积分累加器寄存器种子和换档重启的检测丢失采集和CDR重新启动。 在所描述的实施例中，如果针对不正确的采集轨迹的CDR电路，然后检测到CDR锁的实际丢失，并且通过校正积分累加器种子恢复CDR采集，则采用机制来引起更快的锁定状态丢失。

公开(公告)号：US09106462B1

公开(公告)日：2015-08-11

申请号：US14336986

申请日：2014-07-21

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Mohammad S. Mobin

IPC: H04L25/04 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/03694 ,  H04L2025/037

Abstract: Described embodiments include a process and apparatus that takes into account the operating voltage and temperature (VT) variations of a SERDES receiver implemented in an integrated circuit (IC) or system-on-chip (SoC). An analog equalizer (AEQ) adaptation loop and a decision feedback equalizer (DFE) adaptation loop are disabled after the loops have converged or stabilized the parameters of the AEQ and DFE. While the AFE and DFE adaptation loops are disabled, certain monitor coefficients related to signals corrected by the AFE and DFE are adapted and metrics derived therefrom are generated. The metrics are compared to threshold values to check if they have sufficiently changed over time to warrant re-enabling of the AFE and DFE adaptation loops.

Abstract translation: 所描述的实施例包括考虑在集成电路（IC）或片上系统（SoC）中实现的SERDES接收器的工作电压和温度（VT）变化的过程和装置。 在环路收敛或稳定AEQ和DFE的参数之后，禁用模拟均衡器（AEQ）适配环路和判决反馈均衡器（DFE）适配环路。 当AFE和DFE自适应环路被禁用时，与由AFE和DFE校正的信号有关的某些监视系数被调整，并且产生从其导出的度量。 将度量与阈值进行比较，以检查它们是否随时间发生充分变化，以保证AFE和DFE适配环路的重新启用。

公开(公告)号：US08867602B1

公开(公告)日：2014-10-21

申请号：US14011236

申请日：2013-08-27

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Ye Liu ,  Brett D. Hardy ,  Lane A. Smith

IPC: H03H7/30 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03057

Abstract: A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein the second tap quantization is different from the first tap quantization.

Abstract translation: 公开了抽头系数控制电路和用于控制用于判决反馈均衡器的抽头系数的方法。 该方法包括基于第一抽头量化来调整施加到抽头系数的校正电压，并且检测判决反馈均衡器抽头收敛。 在检测到判定反馈均衡器抽头收敛之后，该方法基于第二抽头量化调整施加到抽头系数的校正电压，其中第二抽头量化与第一抽头量化不同。

公开(公告)号：US08816776B2

公开(公告)日：2014-08-26

申请号：US13675520

申请日：2012-11-13

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H03L7/085 ,  H04L7/033 ,  H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0083 ,  H04L7/033 ,  Y10S331/02

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract translation: 一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。 锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。 作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平 第一率。 可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。