公开(公告)号：US20150319018A1

公开(公告)日：2015-11-05

申请号：US14288838

申请日：2014-05-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Niall Fitzgerald

IPC: H04L25/03 ,  H04L27/01

CPC classification number: G11C29/022 ,  G11C29/028 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03312 ,  H04L25/14 ,  H04L27/01 ,  H04L2025/03592

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract translation: 所描述的实施例在采用数据锁存器的接收机电路中提供调整数据锁存器的调整偏移以解决可能与锁存器的微调相互作用的锁存功能特征（例如，滞后和亚稳态）的电路。 根据所描述的实施例，修整过程在偏移电压斜坡的预选方向上运行，以平均化最终修整偏移选择的滞后和亚稳态的影响。 用于调整修整偏移的电路的累积限幅器“0”和“1”分辨率的不同阈值允许修剪运行次数的显着减少，加速切片器的修整处理，允许每当限幅器空闲时相对快速地确定修整偏移 。

公开(公告)号：US08953665B2

公开(公告)日：2015-02-10

申请号：US13768220

申请日：2013-02-15

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H04L27/01 ,  H04L1/20

CPC classification number: H04L27/01 ,  H04L1/201 ,  H04L1/205

Abstract: In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Abstract translation: 在所描述的实施例中，对串行器/解串器（SerDes）器件的接收路径采用基于数据模式的信号丢失检测（LOS）。 基于模式的LOS检测允许通过各种类型的连接介质检测数据丢失，并且通常对信号衰减不敏感。 更具体地，当采用谨慎的时间判定反馈均衡（DFE）时，一些所描述的实施例公开了用于输入接收数据的不同连接介质上的LOS的可靠的基于模式的检测。

公开(公告)号：US20140132320A1

公开(公告)日：2014-05-15

申请号：US13675520

申请日：2012-11-13

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0083 ,  H04L7/033 ,  Y10S331/02

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract translation: 一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。 锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。 作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平 第一率。 可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。