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公开(公告)号：US4947393A
公开(公告)日：1990-08-07
申请号：US242565
申请日：1988-09-12
CPC分类号： G06F11/0757
摘要： The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.
摘要翻译： 用于接收存储器或逻辑的部分的请求操作的主存储单元或计算机逻辑的逻辑卡被划分为存储体或元件。 当请求操作尝试访问元素之一时，从该元素引起返回忙信号。 本发明的结构产生一个预测的忙信号，该预测的忙信号在同一时间内应该被激活或可操作的。 在新电路中比较返回忙信号和预测忙信号，以验证执行操作的元件实际上是在允许执行所请求的操作的预定时隙期间执行操作。 银行无效的故障信号存储在内部检查陷阱电路中，以供将来参考，当请求者提出后续请求操作时。
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公开(公告)号：US4933908A
公开(公告)日：1990-06-12
申请号：US264113
申请日：1988-10-28
IPC分类号： G11C11/406 , G11C29/02
CPC分类号： G11C29/02 , G11C11/406
摘要： A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory. Whenever a mismatch occurs between the refresh error signal and the refresh request for one of the refresh channels, the validated refresh request signal for that channel will be inoperable, and continued refreshing operation of the memory depends on the supply of the validated refresh request signals through the other channel in which the refresh request signal and the refresh error signals still match.
摘要翻译： 动态随机存取存储器（DRAM）存储器刷新方案利用至少两个单独的刷新通道。 每个通道由一对相同的计数器组成，它们通过两种不同类型的定时链耦合。 定时链中的一个与计数器之一相关联，并产生刷新请求信号，而另一个定时通道产生刷新误差信号。 只要刷新误差信号与刷新请求信号一致，则不存在错误，并且将从该定时信道生成经过验证的刷新请求信号，并提供给或门以刷新存储器的所有存储体。 每当刷新误差信号与刷新信道之一的刷新请求之间发生不匹配时，该信道的经验证的刷新请求信号将是不可操作的，并且存储器的继续刷新操作取决于经过验证的刷新请求信号的供应 刷新请求信号和刷新错误信号仍然匹配的另一个通道。
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公开(公告)号：US4926313A
公开(公告)日：1990-05-15
申请号：US246510
申请日：1988-09-19
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, followed by clearance of the next highest priority latch of the lower priority register sector while the higher priority register is loaded once again. The sequence is repeated until both the higher and lower priority sectors of the register are clear.
摘要翻译： 双优先级保持寄存器使得能够根据优先级的两个阶段将数据传送到具有串行优先级的存储器端口。 首先，清除寄存器的高优先级扇区的所有锁存器。 然后，清除寄存器的低优先级扇区的最高优先级锁存器，而较高优先级寄存器的锁存器加载更多数据。 在清除低优先级锁存器之后，较高优先级寄存器的所有锁存器将再次被清零，随后在较低优先级寄存器扇区的下一个最高优先级锁存器中清零，同时再次加载较高优先级寄存器。 重复该顺序，直到寄存器的较高和较低优先级扇区清除。
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14.发明授权Processor communications bus having address lines selecting different storage locations based on selected control lines 失效处理器通信总线，其具有基于所选择的控制线选择不同存储位置的地址线
公开(公告)号：US5519876A
公开(公告)日：1996-05-21
申请号：US172629
申请日：1993-12-23
CPC分类号： G06F12/063
摘要： A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.
摘要翻译： 总线架构包括地址线，数据线和控制信号，以允许处理器与VLSI门阵列通信。 地址线由VLSI门阵列解释，以根据从处理器接收的控制信号来选择驻留在VLSI门阵列上的多位寄存器或单位指示符。 VLSI门阵列上的双地址解码逻辑检测指示从寄存器读取，写入寄存器，设置，清除或测试指示符的请求的控制信号，并解码所接收的地址，以选择所请求的适当存储位置 功能。
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15.发明授权
公开(公告)号：US5515507A
公开(公告)日：1996-05-07
申请号：US173317
申请日：1993-12-23
申请人： Larry L. Byers , Joseba M. De Subijana , Wayne A. Michaelson , Lloyd E. Thorsbakken , Howard H. Tran
发明人： Larry L. Byers , Joseba M. De Subijana , Wayne A. Michaelson , Lloyd E. Thorsbakken , Howard H. Tran
CPC分类号： G06F11/10
摘要： A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.
摘要翻译： 一种总线架构和相关电路，用于提供处理器与多个门阵列之间的通信，从而正在传送的数据的大小可以是每字32位或36位的全字，或16位或18位的半字 每个字 奇偶校验生成逻辑对要通过总线发送的数据进行操作，以根据所选择的数据字大小从正确的数据位生成奇偶校验值。 奇偶校验逻辑对从总线接收的数据进行操作，以根据所选择的数据字大小检查正确数据位的奇偶性。
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公开(公告)号：US5495598A
公开(公告)日：1996-02-27
申请号：US173598
申请日：1993-12-23
IPC分类号： G06F9/32 , G06F9/38 , G06F11/267 , G06F11/00 , H03M13/00
CPC分类号： G06F9/3804 , G06F11/2236 , G06F9/30058 , G06F9/30094
摘要： A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation. The branch condition is sent to the microprocessor as a signal pulse for a specified duration at a particular time, rather than by changing the level of the signal, thereby allowing communication of the branch condition over only one signal line but still providing for detection of faults in the VSLI gate array or faults inherent in the signal line.
摘要翻译： 一种用于检测用于通过包含可编程微处理器的数据处理系统和由双向总线连接的多个VLSI门阵列来传送用于执行条件转移指令的分支条件的信号线中的卡死故障的方法和装置，由此分支条件是 从驻留在执行异步并在微处理器外部的VLSI门阵列上的存储位置获得。 分支条件与分支目标地址的获取和程序计数器的递增并行获取和评估。 微处理器根据分支条件评估的结果改变指令序列控制。 分支条件作为特定时间的指定持续时间的信号脉冲发送到微处理器，而不是通过改变信号的电平，从而允许在仅一条信号线上通信分支条件，但仍然提供故障的检测 在VSLI门阵列或信号线固有的故障。
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17.发明授权System and method for storing partial blocks of file data in a file cache system by merging partial updated blocks with file block to be written 失效通过将部分更新的块与要写入的文件块合并来将文件数据的部分块存储在文件高速缓存系统中的系统和方法
公开(公告)号：US5555391A
公开(公告)日：1996-09-10
申请号：US172663
申请日：1993-12-23
CPC分类号： G06F12/0866 , G06F12/0804 , G06F2212/312
摘要： A system and method for updating partial blocks of file data stored in a non-volatile storage within a file cache system connected to a host computer system. A first buffer and a last buffer receive from the non-volatile storage the existing portions of the blocks that are to be retained. A write buffer receives new data of a size not equal to an integral multiple of a block from a host computer system. The new data is merged under hardware control with the existing portions contained in the first buffer and the last buffer, thereby updating the cached file.
摘要翻译： 一种用于更新存储在连接到主计算机系统的文件高速缓存系统内的非易失性存储器中的部分文件数据块的系统和方法。 第一缓冲器和最后一个缓冲器从非易失性存储器接收要保留的块的现有部分。 写入缓冲器从主计算机系统接收不等于块的整数倍的大小的新数据。 新数据在硬件控制下与第一个缓冲区和最后一个缓冲区中包含的现有部分进行合并，从而更新缓存的文件。
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18.发明授权
公开(公告)号：US5440604A
公开(公告)日：1995-08-08
申请号：US233842
申请日：1994-04-26
CPC分类号： G06F11/10 , H03K21/40 , G06F2201/88
摘要： A counter system having associated counter error detection circuitry that utilizes the current parity, the previous parity, and a predicted parity for evaluating counter operation is described. In successive count cycles, a predicted parity is utilized, during the next subsequent count cycle is stored in flip-flop as the current parity, and in the next subsequent count cycle is stored a second flip-flop as a previous parity. Circuit are described for performing parity check and parity prediction functions. The previous parity, current parity and predicted parity will not be alike for any binary counter that operates properly. Circuity is described that holds and compares the parity of the Count, the current parity, and the previous parity, during each counter advance cycle and to provide an error signal when the counter is detected to be stuck.
摘要翻译： 描述了具有利用当前奇偶校验，先前奇偶校验和用于评估计数器操作的预测奇偶校验的相关联的计数器错误检测电路的计数器系统。 在连续的计数周期中，利用预测奇偶校验，在下一后续计数周期中作为当前奇偶校验存储在触发器中，并且在下一个后续计数周期中存储第二触发器作为先前奇偶校验。 描述用于执行奇偶校验和奇偶校验预测功能的电路。 以前的奇偶校验，当前奇偶校验和预测奇偶校验值对于任何正常运行的二进制计数器都不会相同。 描述了在每个计数器提前周期期间保持并比较计数，当前奇偶校验和先前奇偶校验的奇偶校验，并且当检测到计数器被卡住时提供错误信号。
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公开(公告)号：US4674032A
公开(公告)日：1987-06-16
申请号：US596203
申请日：1984-04-02
申请人： Wayne A. Michaelson
发明人： Wayne A. Michaelson
CPC分类号： G06F5/16 , G06F13/1615
摘要： A high performance pipelined virtual first-in first-out stack structure having a data stack portion and a split control stack portion is described. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers. An even address read pointer and an odd address read pointer under control of a read pointer control circuit alternates the selection for read out sequentially between the even address and odd address stack registers such that decoding of the memory bank request signals for the next reference can be interleaved with completion of the decoding and prioritization of the current stack register. Advancement of stack register addresses at which writing will take place is under control of a reguest signal. Control of the read pointers for the data stack and the split control stack are responsive to bank acknowledge signals received by the read pointer control circuits.
摘要翻译： 描述具有数据堆栈部分和分割控制堆栈部分的高性能流水线虚拟先进先出堆栈结构。 堆叠结构旨在用于流水线高性能存储单元，其可以管理高达R个输入请求，而不会收到对请求已被兑现的确认。 数据堆栈包含R + 1数据堆栈寄存器，以提供覆盖写保护，以确保至少保护R数据堆栈寄存器免受重写。 分割控制堆栈使用偶数地址和奇数地址堆栈寄存器。 存储器存储器请求信号顺序并交替地存储在偶数地址和奇数地址堆栈寄存器之间。 在读指针控制电路的控制下，偶地址读指针和奇地址读指针在偶数地址和奇地址堆栈寄存器之间交替地选择读出顺序，以便下一个参考的存储器组请求信号的解码可以是 与当前堆栈寄存器的解码和优先级排序完成交织。 提前进行写入的堆栈寄存器地址将受到一个可靠信号的控制。 对于数据堆栈和分离控制堆栈的读指针的控制响应于由读指针控制电路接收的存储体确认信号。
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公开(公告)号：US5612965A
公开(公告)日：1997-03-18
申请号：US573509
申请日：1995-12-15
申请人： Wayne A. Michaelson
发明人： Wayne A. Michaelson
CPC分类号： G06F11/1028 , G06F11/1008 , G06F11/1016
摘要： An apparatus for efficiently detecting errors in a system having a plurality of memory devices. The present invention uses a single parity bit configuration to detect common data errors caused by faulty memory devices including multiple data errors within one memory device. This is accomplished by effectively turning a multiple bit error detection situation into a single bit error detection situation. Thus, instead of allocating a contiguous block of bits to the same memory unit, the present invention allocates bits across all memory units in a round-robin fashion. The parity domains are defined such that multiple errors within one SRAM can be detected despite only using a single bit parity configuration.
摘要翻译： 一种用于有效地检测具有多个存储器件的系统中的错误的装置。 本发明使用单个奇偶校验位配置来检测在一个存储器件内包括多个数据错误的故障存储器件引起的公共数据错误。 这是通过将多位错误检测情况有效地转换为单个位错误检测情况来实现的。 因此，本发明不是将相邻的比特块分配给相同的存储器单元，而是以循环方式分配所有存储器单元中的比特。 奇偶校验域被定义为使得仅使用单个位奇偶校验配置可以检测到一个SRAM内的多个错误。
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