公开(公告)号：US4672240A

公开(公告)日：1987-06-09

申请号：US770486

申请日：1985-08-29

申请人： Teresa B. Smith ,  Philip C. Smith

发明人： Teresa B. Smith ,  Philip C. Smith

IPC分类号： G11C29/00 ,  H03K19/003 ,  H03K19/094

CPC分类号： G11C29/789

摘要： A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder.The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

摘要翻译： 描述存储器冗余电路，其结合有与多个可编程行或列解码器相关联的顺序行或列计数器。 顺序行计数器包括用于每个可编程行解码器的序列电路。序列电路和可编程行解码器包括诸如金属氮化物半导体（MNOS）晶体管的固定和可变阈值晶体管。 响应于地址信号和控制信号来切换可变阈值晶体管的阈值以允许冗余。 还描述了禁用电路以允许去除冗余电路以允许其他电路的重新测试。

公开(公告)号：US4160291A

公开(公告)日：1979-07-03

申请号：US929626

申请日：1978-07-31

申请人： Philip C. Smith ,  John L. Fagan

发明人： Philip C. Smith ,  John L. Fagan

IPC分类号： G11C5/02 ,  G11C8/10 ,  G11C11/30 ,  G11C11/34 ,  G11C16/04 ,  G11C16/08 ,  H03K3/356 ,  H03K19/0185 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C11/30 ,  G11C16/0466 ,  G11C5/025 ,  G11C8/10 ,  H03K19/01855 ,  H03K3/356008

摘要： An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

公开(公告)号：US07989249B2

公开(公告)日：2011-08-02

申请号：US12365284

申请日：2009-02-04

申请人： Nathan Bluzer ,  Silai V. Krishnaswamy ,  Philip C. Smith

发明人： Nathan Bluzer ,  Silai V. Krishnaswamy ,  Philip C. Smith

IPC分类号： H01L21/00

CPC分类号： H01L31/08 ,  B81B3/0081 ,  B81B2201/0207 ,  H01L23/3121 ,  H01L31/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a micro-electrical-mechanical system with thermally isolated active elements. Such a system may embody a bolometer, which is well suited for detecting electromagnetic radiation between 90 GHz and 30 THz while operating at room temperature. The method also discloses a generalized process for manufacturing circuitry incorporating active and passive micro-electrical-mechanical systems in a silicon wafer.

摘要翻译： 一种制造具有热隔离有源元件的微机电系统的方法。 这样的系统可以包含测辐射热计，这适用于在室温下操作时检测90GHz和30Hz之间的电磁辐射。 该方法还公开了一种用于制造在硅晶片中并入有源和无源微机电系统的电路的通用方法。

公开(公告)号：US4533934A

公开(公告)日：1985-08-06

申请号：US192961

申请日：1980-10-02

申请人： Philip C. Smith

发明人： Philip C. Smith

IPC分类号： H01L21/822 ,  H01L21/3213 ,  H01L21/764 ,  H01L21/8246 ,  H01L21/86 ,  H01L23/482 ,  H01L27/04 ,  H01L27/112 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  G11C11/40

CPC分类号： H01L29/78696 ,  H01L21/86 ,  H01L23/4825 ,  H01L27/12 ,  H01L29/78618 ,  H01L29/78657 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor device structure incorporating the edge of silicon island as a surface for diffusing impurities is described to form the drain and source of an MOS transistor and interconnections therebetween to form semiconductor devices such as MOS transistors, variable threshold MNOS transistors, row decoders for use in memories, memory arrays, interconnect crossovers, and high-voltage transistors. A semiconductor process is described for fabricating the above devices utilizing four or five masks.The invention overcomes the problem of high-density integrated circuits by utilizing the edges of silicon islands on an insulating substrate as well as the upper surface of the islands. In addition, contact metallizations are non-critical because of the Schottky barrier diode formed between aluminum and n-type silicon. Both n and p-type semiconductor devices are described.

摘要翻译： 描述了包含硅岛边缘作为扩散杂质的表面的半导体器件结构，以形成MOS晶体管的漏极和源极以及它们之间的互连，以形成半导体器件，例如MOS晶体管，可变阈值MNOS晶体管，行解码器，用于 存储器，存储器阵列，互连交叉和高压晶体管。 描述了使用四个或五个掩模来制造上述器件的半导体工艺。 本发明通过利用绝缘基板上的硅岛的边缘以及岛的上表面来克服高密度集成电路的问题。 此外，由于在铝和n型硅之间形成肖特基势垒二极管，接触金属化是非关键的。 描述n型和p型半导体器件。