公开(公告)号：US06355560B1

公开(公告)日：2002-03-12

申请号：US09209434

申请日：1998-12-10

申请人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

发明人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

IPC分类号： H01L214763

CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

摘要翻译： 本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。 所得到的CVD / PVD金属层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

公开(公告)号：US06726776B1

公开(公告)日：2004-04-27

申请号：US09370599

申请日：1999-08-09

申请人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

发明人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

IPC分类号： C23C1600

CPC分类号： H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  Y10S414/139

摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

摘要翻译： 本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。 所得到的CVD / PVD金属层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

公开(公告)号：US06605531B1

公开(公告)日：2003-08-12

申请号：US09127010

申请日：1998-07-31

申请人： Ted Guo ,  Wei Shi ,  Liang-Yuh Chen

发明人： Ted Guo ,  Wei Shi ,  Liang-Yuh Chen

IPC分类号： H01L214763

CPC分类号： H01L21/2855 ,  H01L21/28556 ,  H01L21/76882

摘要： The present invention provides a method for filling an aperture on a substrate by depositing a metal film on the substrate of insufficient thickness to fill the sub half-micron aperture and then annealing the substrate in a low pressure chamber at a temperature below a melting point of the deposited metal film. The present invention further provides forming a planarized film over the void-free aperture by physical vapor depositing a metal film over the annealed film.

摘要翻译： 本发明提供了一种通过在基板上沉积不足厚度的金属膜来填充基板上的孔的方法，以填充次半微米孔径，然后在低压室内在低于熔点的温度下将基板退火 沉积金属膜。 本发明还提供了通过在退火膜上物理气相沉积金属膜而在无空隙孔上形成平坦化膜。

公开(公告)号：US6110828A

公开(公告)日：2000-08-29

申请号：US791653

申请日：1996-12-30

申请人： Ted Guo ,  Liang-Yuh Chen ,  Suchitra Subrahmanyan

发明人： Ted Guo ,  Liang-Yuh Chen ,  Suchitra Subrahmanyan

IPC分类号： H01L21/285 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/443

CPC分类号： H01L21/76879

摘要： The present invention generally provides a method of forming a structure having a selective CVD metal plug with a continuous barrier layer formed thereon. More particularly, the present invention applies a thin layer of warm PVD metal over a selective CVD metal plug and adjacent nodules on the dielectric field to planarize the metal surface. A barrier is then deposited over the planarized metal surface. Therefore, the invention provides the advantages of having (1) void-free, sub-half micron selective CVD metal via plugs and interconnects, and (2) a reduced number of process steps without the use of CMP, and (3) barrier layers over the metal plugs to improve the electromigration resistance of the metal.

摘要翻译： 本发明通常提供一种形成具有在其上形成有连续势垒层的选择性CVD金属塞的结构的方法。 更具体地说，本发明在选择性CVD金属塞上和在电介质场上的相邻结节上施加薄层的温热PVD金属以使金属表面平坦化。 然后在平坦化的金属表面上沉积屏障。 因此，本发明提供了具有（1）无空隙的半微米选择性CVD金属通孔塞和互连件的优点，和（2）减少数量的工艺步骤而不使用CMP，以及（3）阻挡层 在金属插头上提高金属的电迁移阻力。

公开(公告)号：US06518176B2

公开(公告)日：2003-02-11

申请号：US09092747

申请日：1998-06-05

申请人： Ted Guo ,  Liang-Yuh Chen ,  Suchitra Subrahmanyan ,  Roderick C. Mosely

发明人： Ted Guo ,  Liang-Yuh Chen ,  Suchitra Subrahmanyan ,  Roderick C. Mosely

IPC分类号： H01L2144

CPC分类号： H01L21/76876 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact level via and a method of performing selective deposition of a barrier layer to form a contact level via for selective aluminum metallization. Specifically, the method forms a self-aligned silicide region by depositing titanium atop a structure containing a contact level via, converting the titanium in the contact regions into titanium silicide, removing the unreacted titanium, and performing nitridation of the titanium silicide to complete a barrier layer located in only the contact region of the via. Once the barrier layer is formed, the layer can be optionally fortified through oxygen stuffing to create an effective barrier layer for aluminum metallization.

摘要翻译： 接触电平通孔和执行选择性沉积阻挡层以形成用于选择性铝金属化的接触电平通路的方法。 具体地，该方法通过在包含接触电平通孔的结构上方沉积钛而形成自对准硅化物区域，将接触区域中的钛转化为硅化钛，除去未反应的钛，并进行硅化钛的氮化以完成阻挡层 层位于通孔的接触区域中。 一旦形成了阻挡层，就可以通过氧气填充来选择性地强化该层，以产生用于铝金属化的有效阻挡层。

公开(公告)号：US06509274B1

公开(公告)日：2003-01-21

申请号：US09632486

申请日：2000-08-04

申请人： Ted Guo ,  Jing-Pei Chou ,  Liang-Yuh Chen ,  Roderick C. Mosely

发明人： Ted Guo ,  Jing-Pei Chou ,  Liang-Yuh Chen ,  Roderick C. Mosely

IPC分类号： H01L21302

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76882

摘要： A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.

摘要翻译： 一种用于在半导体衬底中的铝填充通孔上形成铝线的方法，其可以补偿所填充的通孔和线之间的一些不对准。 通过在衬底上交替沉积衬垫阻挡层和铝层，可以使用不同的蚀刻化学性质，其可以各向异性地蚀刻用于形成线的铝层，而不会在铝填充的通孔中蚀刻空隙。

公开(公告)号：US6077781A

公开(公告)日：2000-06-20

申请号：US620405

申请日：1996-03-22

申请人： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

发明人： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

IPC分类号： H01L21/285 ,  C23C14/56 ,  C23C16/54 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC分类号： C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectric layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

摘要翻译： 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。 在本发明的一个方面中，在导电部件上形成电介质层。 然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以露出孔底板上的下面的导电构件。 然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。

公开(公告)号：US06458684B1

公开(公告)日：2002-10-01

申请号：US09497390

申请日：2000-02-03

申请人： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

发明人： Ted Guo ,  Liang-Yuh Chen ,  Mehul Naik ,  Roderick C. Mosely

IPC分类号： H01L2144

CPC分类号： C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

摘要翻译： 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在半微米孔径宽度应用中形成连续的无空隙触点或通孔。 在本发明的一个方面中，在导电部件上形成电介质层。 然后在蚀刻通过成核和电介质层的高纵横比孔之前将薄的成核层沉积到介电层上，以暴露孔底板上的下面的导电构件。 然后将CVD金属层沉积到结构上以实现孔内的选择性沉积，同时优选地还在场上形成覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。

公开(公告)号：US07112528B2

公开(公告)日：2006-09-26

申请号：US10367214

申请日：2003-02-13

申请人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

发明人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L21/28562 ,  H01L21/76879

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

公开(公告)号：US06537905B1

公开(公告)日：2003-03-25

申请号：US08778205

申请日：1996-12-30

申请人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

发明人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC分类号： H01L214763

CPC分类号： H01L21/28562 ,  H01L21/76879

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其通过填充形成在阻挡层内的金属线，优选铜，并入选择性化学气相沉积铝（CVD Al）。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。