公开(公告)号：US06368940B1

公开(公告)日：2002-04-09

申请号：US09642325

申请日：2000-08-21

申请人： Jürgen Amon ,  Albrecht Kieslich

发明人： Jürgen Amon ,  Albrecht Kieslich

IPC分类号： H01L2176

CPC分类号： H01L21/76237

摘要： A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.

摘要翻译： 微电子结构的制造方法包括至少在半导体衬底的主区域的区域中将氮注入到具有沟槽的半导体衬底中。 该植入旨在以这样一种方式进行，使得主要区域的氮浓度明显大于沟槽的侧壁处的氮浓度。 结果，在随后氧化半导体衬底期间，与侧壁相比，可以在主区域上形成更薄的氧化物层。 氧化物层在主区域和侧壁之间的边缘区域中具有均匀的过渡。 在半导体衬底的氧化之前将氮掺杂导致主区域上的均匀的氧化物层厚度。

公开(公告)号：US20050196689A1

公开(公告)日：2005-09-08

申请号：US11071571

申请日：2005-03-04

申请人： Christoph Nolscher ,  Rainer Pforr ,  Mario Hennig ,  Albrecht Kieslich

发明人： Christoph Nolscher ,  Rainer Pforr ,  Mario Hennig ,  Albrecht Kieslich

IPC分类号： G03F1/30 ,  G03F7/20 ,  G03F9/00

CPC分类号： G03F1/30

摘要： A mask level layout has an arrangement of lines and spaces with the spaces interconnected by a further space. The spaces are alternately acted upon with a phase deviation with respect to the spaces, where a phase edge between spaces acted upon differently arises in the region of the further space. Alternatively, the connecting space within the layout may be filled with dark regions. An additional space is inserted in a second layout representing a further mask of the same mask set. The additional space enables formation of an insulating region on a semiconductor substrate at the location where formation of a continuous isolation trench is not possible due to the phase edges or dark regions within originally connecting spaces of the first mask. The first mask can be embodied as a hybrid mask with structures according to the principle of alternating phase masks with a large process window.

摘要翻译： 掩模级别布局具有线和空间的布置，空间通过另外的空间互连。 空间交替地以相对于空间的相位偏移地起作用，其中空间之间的相位在另外空间的区域中不同地起作用。 或者，布局中的连接空间可以用黑色区域填充。 在另一个布局中插入一个额外的空间，表示相同掩模集的另一掩码。 附加空间使得能够在由于第一掩模的原始连接空间内的相位边缘或暗区域而不可能形成连续隔离沟槽的位置处在半导体衬底上形成绝缘区域。 第一个掩模可以实现为具有根据具有大工艺窗口的交替相位掩模原理的结构的混合掩模。

公开(公告)号：US06864170B2

公开(公告)日：2005-03-08

申请号：US10432770

申请日：2001-11-28

申请人： Falko Höhnsdorf ,  Albrecht Kieslich ,  Detlef Weber

发明人： Falko Höhnsdorf ,  Albrecht Kieslich ,  Detlef Weber

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor substrate and etching trenches in the first insulating layer. Metallic interconnects are formed in the trenches by metallization. The semiconductor structure is polished to remove metal from the first insulating layer, leaving behind metal in the trenches. A portion of the first insulating layer between the first and second metallic interconnects is etched so that the first and second metallic interconnects project above the first insulating layer. A second insulating layer is applied on the substrate such that the metallic interconnects project into the second insulating layer. The second insulating layer has a relative permittivity that is lower than the relative permittivity of the first insulating layer.

摘要翻译： 一种用于减小半导体结构上的互连之间的电容耦合的方法包括在半导体衬底上制造第一绝缘层并蚀刻第一绝缘层中的沟槽。 通过金属化在沟槽中形成金属互连。 抛光半导体结构以从第一绝缘层去除金属，留下沟槽中的金属。 在第一和第二金属互连之间的第一绝缘层的一部分被蚀刻，使得第一和第二金属互连突出在第一绝缘层之上。 在基板上施加第二绝缘层，使得金属互连突出到第二绝缘层中。 第二绝缘层的相对介电常数低于第一绝缘层的相对介电常数。

公开(公告)号：US06753236B2

公开(公告)日：2004-06-22

申请号：US10233686

申请日：2002-09-03

申请人： Klaus Feldner ,  Werner Graf ,  Albrecht Kieslich ,  Hermann Sachse

发明人： Klaus Feldner ,  Werner Graf ,  Albrecht Kieslich ,  Hermann Sachse

IPC分类号： H01L2176

CPC分类号： H01L21/31055 ,  H01L21/76229 ,  H01L27/10844

摘要： A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

摘要翻译： 描述了沉积在半导体本体上的隔离层的表面的平坦化方法。 隔离层具有低电平的区域被块掩模覆盖，以便能够以更高的电平选择性地蚀刻隔离层的区域。