公开(公告)号：US06753236B2

公开(公告)日：2004-06-22

申请号：US10233686

申请日：2002-09-03

申请人： Klaus Feldner ,  Werner Graf ,  Albrecht Kieslich ,  Hermann Sachse

发明人： Klaus Feldner ,  Werner Graf ,  Albrecht Kieslich ,  Hermann Sachse

IPC分类号： H01L2176

CPC分类号： H01L21/31055 ,  H01L21/76229 ,  H01L27/10844

摘要： A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

摘要翻译： 描述了沉积在半导体本体上的隔离层的表面的平坦化方法。 隔离层具有低电平的区域被块掩模覆盖，以便能够以更高的电平选择性地蚀刻隔离层的区域。

公开(公告)号：US07217610B2

公开(公告)日：2007-05-15

申请号：US10485308

申请日：2002-07-30

申请人： Werner Graf ,  Albrecht Kieslich

发明人： Werner Graf ,  Albrecht Kieslich

IPC分类号： H01L21/8238 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

摘要： A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

摘要翻译： 公开了用于在半导体衬底中集成用于存储器和逻辑应用的场效应晶体管的方法。 栅极电介质和半导体层沉积在逻辑区域和存储区域中的整个区域上。 从这些层，形成存储区域中的栅电极，注入源区和漏区，并且用绝缘材料以平坦化方式覆盖存储区。 之后，栅极电极由逻辑区域中的半导体层和栅极电介质形成。

公开(公告)号：US10550765B2

公开(公告)日：2020-02-04

申请号：US16345315

申请日：2017-10-26

申请人： Peter Ortmann ,  Werner Graf

发明人： Peter Ortmann ,  Werner Graf

IPC分类号： F01K3/00 ,  F02C6/14 ,  F28D17/00 ,  F02C1/04 ,  F01K25/00

摘要： An energy storage device having: a high-temperature regenerator containing a solid, particularly porous storage material (S); a working gas (A) as the heat transfer medium to transfer heat between the storage material (S) and the working gas (A) flowing through; and a charging circuit and a discharging circuit for the working gas (A). The charging circuit is designed such that starting from a pre-heating unit at least one first heat transfer duct of a recuperator, a first compressor (HO), the high-temperature regenerator, a second heat transfer duct of the recuperator and then a first expander are interconnected, thus forming a circuit, so as to conduct fluid. The first compressor is coupled with the first expander, and the first compressor forms part of a first piston machine (K1) and the first expander forms part of a second piston machine (K2), the piston machines (K1, K2) being operable either as a compressor or as an expander such that the first compressor of the charging circuit forms a second expander in the discharging circuit and that the first expander of the charging circuit forms a second compressor in the discharging circuit. The high-temperature regenerator can be connected to either the charging circuit or the discharging circuit to conduct fluid and can be controlled such that the high-temperature regenerator, the compressor and the expander form either part of the charging circuit or part of the discharging circuit. The charging circuit, the discharging circuit and the high-temperature regenerator have the same working gas (A) so that the working gas (A) comes into direct contact with the storage material of the high-temperature regenerator both in the charging circuit and in the discharging circuit.

公开(公告)号：US07838928B2

公开(公告)日：2010-11-23

申请号：US12134740

申请日：2008-06-06

申请人： Werner Graf ,  Lars Heineck ,  Martin Popp

发明人： Werner Graf ,  Lars Heineck ,  Martin Popp

IPC分类号： H01L29/792

CPC分类号： H01L21/76232 ,  H01L21/743 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

摘要翻译： 在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。 在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。 大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。

公开(公告)号：US20100090285A1

公开(公告)日：2010-04-15

申请号：US12251864

申请日：2008-10-15

申请人： Werner Graf ,  Clemens Fitz

发明人： Werner Graf ,  Clemens Fitz

IPC分类号： H01L27/088 ,  H01L23/48 ,  H01L21/76

CPC分类号： H01L21/743 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/66636 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.

摘要翻译： 集成电路包括具有埋入的第一和突出的第二部分的接触结构。 掩埋的第一部分布置在形成于半导体结构中并与半导体结构直接接触的空腔中。 突出的第二部分布置在半导体结构的主表面上方，并且与与半导体结构的主表面间隔开或分离的导电结构直接接触。 绝缘体结构布置在接触结构的下方并直接接触。

公开(公告)号：US20080150141A1

公开(公告)日：2008-06-26

申请号：US11652255

申请日：2007-01-11

申请人： Werner Graf ,  Andreas Thies ,  Marco Lepper ,  Momtchil Stavrev

发明人： Werner Graf ,  Andreas Thies ,  Marco Lepper ,  Momtchil Stavrev

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate with a main surface; forming a wiring metal layer above said main surface; forming a doped getter layer on said wiring metal layer; and forming at least one additional wiring metal layer on said doped getter layer. The present invention also provides a corresponding integrated semiconductor structure and a semiconductor memory device.

摘要翻译： 本发明提供一种用于集成半导体结构的制造方法，包括以下步骤：提供具有主表面的半导体衬底; 在所述主表面上形成布线金属层; 在所述布线金属层上形成掺杂的吸气剂层; 以及在所述掺杂的吸气剂层上形成至少一个附加的布线金属层。 本发明还提供了相应的集成半导体结构和半导体存储器件。

公开(公告)号：US20060276019A1

公开(公告)日：2006-12-07

申请号：US11503557

申请日：2006-08-11

申请人： Werner Graf ,  Henning Haffner ,  Johannes Kowalewski ,  Lars Heineck

发明人： Werner Graf ,  Henning Haffner ,  Johannes Kowalewski ,  Lars Heineck

IPC分类号： H01L21/3205 ,  H01L21/44

CPC分类号： H01L27/10888 ,  H01L21/76897

摘要： The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

摘要翻译： 本发明涉及一种用于在晶片上生产触点的方法，优选借助于光刻工艺。 优选实施例提供一种克服复杂点/孔光刻工艺的缺点的方法，并且避免了工艺复杂性的任何增加。 该方法的实现是使用两层延伸的条状结构来构造触点。 第一层中的带状结构相对于第二层中的带状结构以预定角度旋转，并且触点形成在两层中条带结构的相互重叠的区域中。

公开(公告)号：US5582381A

公开(公告)日：1996-12-10

申请号：US441202

申请日：1995-05-15

申请人： Werner Graf ,  Simon Frank ,  Karl Baumann

发明人： Werner Graf ,  Simon Frank ,  Karl Baumann

IPC分类号： B60N2/07 ,  F16C29/12 ,  F16M13/00

CPC分类号： F16C29/02 ,  B60N2/071 ,  B60N2/0715 ,  B60N2/072 ,  B60N2/075 ,  B60N2205/20

摘要： Play-free longitudinal guiding means having rails than run inside each other, namely a lower rail and an upper rail that can be displaced in a sliding manner with respect to the lower rail, for securing seats in vehicles such as private cars. The play-free longitudinal guiding means is such that the lower rail features along its length wall parts that have the shape of alignment grooves, and the upper rail features wall parts which run parallel to the wall parts of the lower rail and are shaped into an alignment groove, and the alignment grooves of the upper and lower rails face each other and form a sliding alignment channel. In the sliding channel there are sliding elements which in the free-standing condition exhibit a larger cross-section than in the installed condition, and the sliding elements guide the lower and upper rails without any play.

摘要翻译： 具有比彼此相对运行的轨道的无游隙的纵向引导装置，即可以相对于下轨道滑动地移位的下轨道和上轨道，用于将座椅固定在诸如私家车辆的车辆中。 无轨道纵向引导装置使得下轨道沿其长度壁部分具有对准凹槽的形状，并且上轨道具有平行于下轨道的壁部分延伸并且成形为 上下导轨的对准槽彼此面对并形成滑动对准通道。 在滑动通道中，存在滑动元件，其在独立状态下表现出比在安装状态下更大的横截面，并且滑动元件引导下轨道和上轨而没有任何游隙。

公开(公告)号：US07361974B2

公开(公告)日：2008-04-22

申请号：US11388234

申请日：2006-03-23

申请人： Werner Graf

发明人： Werner Graf

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76829 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a planarisation layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said planarisation layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished planarisation layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substrate contact area adjacent to said gate stack in said second region or a contact area in said gate stack; selectively removing said hardmask layer and said sacrificial plug in a single etch step, whereby another contact hole is formed between two adjacent gate stacks in said first region; removing said isolation layer on the bottom of said another contact hole such that the substrate is exposed; and filling said contact hole and said another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在第一区域中具有多个栅极叠层的半导体衬底和在第二区域中的至少一个栅极叠层; 形成由在所述第一区域中的两个相邻栅极叠层之间的隔离层围绕的第一材料制成的牺牲插塞; 在所述第一区域中的所述多个栅极堆叠上沉积平面化层，并且在所述第二区域中沉积所述至少一个栅极堆叠; 抛光所述平面化层，使得所述牺牲塞的上表面露出; 在所述后抛光平面化层上形成由所述第一材料制成的结构化硬掩模层，所述结构化硬掩模层与所述牺牲塞邻接，并且在所述第二区域中具有至少一个开口; 在所述第二区域的所述至少一个开口下方的所述第二区域内形成至少一个接触孔，所述至少一个接触孔暴露在所述第二区域中的所述栅极堆叠附近的衬底接触区域或所述栅极叠层中的接触区域; 在单个蚀刻步骤中选择性地去除所述硬掩模层和所述牺牲塞，由此在所述第一区域中的两个相邻的栅叠层之间形成另一个接触孔; 去除所述另一个接触孔的底部上的所述隔离层，使得所述衬底露出; 以及用相应的接触插塞填充所述接触孔和所述另一个接触孔。

公开(公告)号：US20070224810A1

公开(公告)日：2007-09-27

申请号：US11388234

申请日：2006-03-23

申请人： Werner Graf

发明人： Werner Graf

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76829 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888 ,  H01L27/10894

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a sacrificial plug made of a first material surrounded by an isolation layer between two adjacent gate stacks in the first region; depositing a polarization layer over said plurality of gate stacks in said first region and said at least one gate stack in said second region; backpolishing said polarization layer such that the upper surface of said sacrificial plug is exposed; forming a structured hardmask layer made of said first material on said backpolished polarization layer which structured hardmask layer adjoins said sacrificial plug and has at least one opening in said second region; forming at least one contact hole in said second region under said at least one opening in said second region, said at least one contact hole exposing a substrate contact area adjacent to said gate stack in said second region or a contact area in said gate stack; selectively removing said hardmask layer and said sacrificial plug in a single etch step, whereby another contact hole is formed between two adjacent gate stacks in said first region; removing said isolation layer on the bottom of said another contact hole such that the substrate is exposed; and filling said contact hole and said another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在第一区域中具有多个栅极叠层的半导体衬底和在第二区域中的至少一个栅极叠层; 形成由在所述第一区域中的两个相邻栅极叠层之间的隔离层围绕的第一材料制成的牺牲插塞; 在所述第一区域中的所述多个栅极堆叠上沉积偏振层，并在所述第二区域中沉积所述至少一个栅极堆叠; 反向抛光所述偏振层，使得所述牺牲塞的上表面露出; 在所述后抛光偏振层上形成由所述第一材料制成的结构化硬掩模层，所述结构化硬掩模层与所述牺牲插塞相邻，并且在所述第二区域中具有至少一个开口; 在所述第二区域的所述至少一个开口下方的所述第二区域内形成至少一个接触孔，所述至少一个接触孔暴露在所述第二区域中的所述栅极堆叠附近的衬底接触区域或所述栅极叠层中的接触区域; 在单个蚀刻步骤中选择性地去除所述硬掩模层和所述牺牲塞，由此在所述第一区域中的两个相邻的栅叠层之间形成另一个接触孔; 去除所述另一个接触孔的底部上的所述隔离层，使得所述衬底露出; 以及用相应的接触插塞填充所述接触孔和所述另一个接触孔。