公开(公告)号：US06753236B2

公开(公告)日：2004-06-22

申请号：US10233686

申请日：2002-09-03

申请人： Klaus Feldner ,  Werner Graf ,  Albrecht Kieslich ,  Hermann Sachse

发明人： Klaus Feldner ,  Werner Graf ,  Albrecht Kieslich ,  Hermann Sachse

IPC分类号： H01L2176

CPC分类号： H01L21/31055 ,  H01L21/76229 ,  H01L27/10844

摘要： A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

摘要翻译： 描述了沉积在半导体本体上的隔离层的表面的平坦化方法。 隔离层具有低电平的区域被块掩模覆盖，以便能够以更高的电平选择性地蚀刻隔离层的区域。

公开(公告)号：US5840625A

公开(公告)日：1998-11-24

申请号：US726443

申请日：1996-10-04

申请人： Klaus Feldner

发明人： Klaus Feldner

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/538 ,  H01L21/28

CPC分类号： H01L21/76847 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： An improved integrated circuit interconnection for interconnecting at least two conductive regions within an integrated circuit, and method for producing the same. The interconnection includes a tungsten layer and a barrier layer to provide a low contact resistance within the interconnection and between the conductive regions and the interconnection. The interconnection also includes an aluminum layer for providing a low sheet resistance in the current path between the two conductive regions. Thus the invention combines the advantages of an all tungsten interconnection with those of a tungsten capsuled aluminum interconnection.

摘要翻译： 用于互连集成电路内的至少两个导电区域的改进的集成电路互连及其制造方法。 互连包括钨层和阻挡层，以在互连内和导电区域与互连之间提供低接触电阻。 互连还包括铝层，用于在两个导电区域之间的电流路径中提供低的薄层电阻。 因此，本发明将所有钨互连的优点与钨封壳铝互连的优点相结合。

公开(公告)号：US07008849B2

公开(公告)日：2006-03-07

申请号：US10724903

申请日：2003-12-01

申请人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

发明人： Grit Schwalbe ,  Kae-Horng Wang ,  Klaus Feldner ,  Elard Stein Von Kamienski

IPC分类号： H01L21/8236

CPC分类号： H01L27/11568 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/112

摘要： A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.

摘要翻译： 一种用于在存储单元阵列中提供位线触点的方法包括沿第一方向布置的多个位线，位线由绝缘层覆盖，多个字线沿垂直于位线上方的第一方向的第二方向布置，以及 位于位线和字线彼此交叉的点处的存储单元。 根据本发明的第一方面，在未被字线覆盖的部分处，从位线移除隔离层，而位线之间的区域保持不受影响。 或者，从整个电池阵列中去除绝缘层。 然后，在位线的露出部分上设置导电材料。 该方法用于在氮化物只读存储器（NROM TM））芯片中提供位线触点。

公开(公告)号：US06300235B1

公开(公告)日：2001-10-09

申请号：US08884861

申请日：1997-06-30

申请人： Klaus Feldner ,  Virinder Grewal ,  Bernd Vollmer ,  Rainer Florian Schnabel

发明人： Klaus Feldner ,  Virinder Grewal ,  Bernd Vollmer ,  Rainer Florian Schnabel

IPC分类号： H01L2144

CPC分类号： H01L21/76808

摘要： An improved method of performing a dual damascene etch through a layer stack disposed above a substrate. The layer stack includes an underlying device layer and an insulating layer disposed above the underlying device layer. The method includes forming a trench in a top surface of the insulating layer such that the trench is positioned over the underlying device layer and separated therefrom by insulating material at a bottom of the trench. The method also includes, depositing flowable oxide over the top surface of the insulating layer and into the trench followed by planarizing the flowable oxide down to about a level of the top surface of the insulating layer. Further, the method includes, etching through the flowable oxide within the trench and through insulating material at the bottom of the trench down to the underlying device layer to form a via.

摘要翻译： 通过设置在衬底上方的层堆栈执行双镶嵌蚀刻的改进方法。 层叠层包括下层器件层和设置在下层器件层上方的绝缘层。 该方法包括在绝缘层的顶表面中形成沟槽，使得沟槽位于下面的器件层上方并且通过沟槽底部的绝缘材料与其隔开。 该方法还包括：将可流动氧化物沉积在绝缘层的顶表面上并进入沟槽中，然后将可流动的氧化物平坦化，直到绝缘层的顶表面的大约一个水平。 此外，该方法包括：蚀刻穿过沟槽内的可流动氧化物并且通过沟槽底部的绝缘材料向下蚀刻到下面的器件层以形成通孔。

公开(公告)号：US5822875A

公开(公告)日：1998-10-20

申请号：US867772

申请日：1997-06-02

申请人： Klaus Feldner

发明人： Klaus Feldner

IPC分类号： G01B3/04 ,  G01B15/00

CPC分类号： G01B3/04 ,  G01B15/00 ,  H01J2237/2816

摘要： A set of ruled devices and method for measuring an actual dimension of a specimen displayed as a magnified image by a magnification system such as a scanning electron microscope having a plurality of selected magnification factors. The magnified image includes dimensions that correspond to a predetermined selected magnification. A set of ruled devices is provided, whereby each ruled device includes indicia that corresponds to one of the magnification factors. A ruled device that corresponds to the predetermined selected magnification is selected. The dimension of the image is measured with the selected ruled device, whereby the indicia of the selected ruled device indicates the actual dimension of the specimen.

摘要翻译： 一组统计装置和方法，用于通过具有多个选择的放大系数的扫描电子显微镜等放大系统来测量显示为放大图像的样本的实际尺寸。 放大图像包括对应于预定的选定倍率的尺寸。 提供了一组排列的装置，其中每个划线装置包括对应于一个放大因子的标记。 选择对应于预定选择的放大倍数的刻线装置。 图像的尺寸用所选定的装置测量，由此所选定的装置的标记表示样品的实际尺寸。

公开(公告)号：US06016008A

公开(公告)日：2000-01-18

申请号：US024998

申请日：1998-02-17

申请人： Klaus Feldner

发明人： Klaus Feldner

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/538 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76847 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002

摘要： An improved integrated circuit interconnection for interconnecting at least two conductive regions within an integrated circuit, and method for producing the same. The interconnection includes a tungsten layer and a barrier layer to provide a low contact resistance within the interconnection and between the conductive regions and the interconnection. The interconnection also includes an aluminum layer for providing a low sheet resistance in the current path between the two conductive regions. Thus the invention combines the advantages of an all tungsten interconnection with those of a tungsten capsuled aluminum interconnection.

摘要翻译： 用于互连集成电路内的至少两个导电区域的改进的集成电路互连及其制造方法。 互连包括钨层和阻挡层，以在互连内和导电区域与互连之间提供低接触电阻。 互连还包括铝层，用于在两个导电区域之间的电流路径中提供低的薄层电阻。 因此，本发明将所有钨互连的优点与钨封壳铝互连的优点相结合。

公开(公告)号：US06638814B1

公开(公告)日：2003-10-28

申请号：US10031743

申请日：2002-01-23

申请人： Albrecht Kieslich ,  Klaus Feldner ,  Herbert Benzinger

发明人： Albrecht Kieslich ,  Klaus Feldner ,  Herbert Benzinger

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/10829

摘要： A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件具有带存储电容器的第一区域和具有由绝缘体包围的至少一个阱的第二区域。 该方法通过在第一区域中形成沟槽和在第二区域中形成至少一个沟槽而形成存储电容器和绝缘体，并且沟槽具有至少2μm的深度。 处理第一区域中的沟槽以提供由电介质隔开的第一和第二电极以形成电容器，并且第二区域中的每个沟槽提供围绕第二区域中的任何孔的绝缘体。