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11.发明授权Integrated circuit environment initialization according to information stored within the integrated circuit 失效根据存储在集成电路内的信息，集成电路环境初始化公开(公告)号：US07996693B2
公开(公告)日：2011-08-09
申请号：US12277365
申请日：2008-11-25
IPC分类号： G06F1/26
CPC分类号： G06F1/206
摘要： A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
摘要翻译： 一种用于根据存储在集成电路的非易失性存储器中的信息自动初始化系统的操作设置的方法，使得当系统运行时系统满足可能是微处理器的集成电路的操作要求 。 在制造测试期间，集成电路的环境要求被确定并存储在集成电路的非易失性存储器中。 在系统初始化期间，从集成电路读取的测试值确定所需的工作电压，频率和冷却要求等环境控制值。 这些值由系统的接口从集成电路的接口读取。 系统设置由值控制以提供所需的操作环境，并且可以在系统内捕获值以用于后续操作和初始化序列。
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公开(公告)号：US07996346B2
公开(公告)日：2011-08-09
申请号：US11959520
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
CPC分类号： G06F9/5083
摘要： A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.
摘要翻译： 一个包含自动工作负载分配的多处理器系统。 当线程在多处理器系统中执行时，操作系统或管理程序将持续学习线程的执行特性，并将信息保存在线程特定的控制块中。 执行特性用于生成线程性能数据。 当线程执行时，操作系统会持续使用性能数据来将线程引导到最高效执行工作负载的内核。
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公开(公告)号：US07389195B2
公开(公告)日：2008-06-17
申请号：US11278303
申请日：2006-03-31
IPC分类号： G01R31/00
CPC分类号： G01R31/2868
摘要： A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
摘要翻译： 提供计算机实现的方法，数据处理系统和计算机可用代码用于多处理器的老化测试。 过程识别与多处理器相关联的多个处理器核心的功率管理数据集。 该过程基于电源管理数据集选择多个处理器核中的一个或多个来形成选定的一组处理器核。 该过程在所选的一组处理器核心上启动老化测试。 响应于确定多个处理器核心中的所有处理器核心未被选择，该过程重复上述选择和启动步骤，直到所有处理器核心已被选择为止。
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14.发明授权Multicore processor and method of use that adapts core functions based on workload execution 失效基于工作负载执行的多核处理器和使用方法可以调整核心功能公开(公告)号：US08645673B2
公开(公告)日：2014-02-04
申请号：US13613936
申请日：2012-09-13
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。
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15.发明授权Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict 有权通过在发生冲突后由主要组件生成的寄存器和内存值重新启动失败的离散可执行子组件的执行来解决冲突公开(公告)号：US08544006B2
公开(公告)日：2013-09-24
申请号：US11959821
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译： 一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令， 并分配空闲核心以执行推测性指令。
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16.发明授权Method and apparatus for providing updated firmware in a data processing system 失效用于在数据处理系统中提供更新的固件的方法和装置
公开(公告)号：US5878256A
公开(公告)日：1999-03-02
申请号：US777844
申请日：1991-10-16
CPC分类号： G06F11/1433
摘要： A programmable firmware store for a personal computer system includes a plurality of nonvolatile alterable electronic memories connected in a mutually paralleled circuit arrangement. The memories are connected to a controller that controls the memories to read firmware from and write firmware into the electronic memories, and to write-protect at least one of the memories. Any memory can be write-protected as initially selected by a user or technician of the system. The initial selection can be changed easily to write-protect another of the memories. The firmware in one memory includes code for checking the validity of firmware stored in another memory, and for selecting one or the other of the memories dependent upon a version code of the firmware. The controller also includes an update code for updating the firmware in a selected memory.
摘要翻译： 用于个人计算机系统的可编程固件存储器包括以相互平行的电路布置连接的多个非易失性可变电子存储器。 存储器连接到控制器，其控制存储器以从固件读取固件并将固件写入电子存储器，并且对至少一个存储器进行写保护。 任何存储器可以由系统的用户或技术人员最初选择的写保护。 初始选择可以轻松改变，以便对另一个存储器进行写保护。 一个存储器中的固件包括用于检查存储在另一个存储器中的固件的有效性的代码，以及用于根据固件的版本代码选择一个或另一个存储器。 控制器还包括用于更新选定存储器中的固件的更新代码。
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17.发明授权Multicore processor and method of use that adapts core functions based on workload execution 有权基于工作负载执行的多核处理器和使用方法可以调整核心功能公开(公告)号：US08327126B2
公开(公告)日：2012-12-04
申请号：US12197357
申请日：2008-08-25
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译： 处理器具有多个核心，每个核心具有相关功能以支持处理器操作。 通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。 例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。 作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。
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18.发明授权Optimizing execution of single-threaded programs on a multiprocessor managed by compilation 有权在编译器管理的多处理器上优化单线程程序的执行公开(公告)号：US08312455B2
公开(公告)日：2012-11-13
申请号：US11960021
申请日：2007-12-19
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译： 一种用于优化多核处理器上单个线程程序的执行的方法。 该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以供所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。
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19.发明授权Method and system for system performance optimization via heuristically optimized buses 有权通过启发式优化的总线进行系统性能优化的方法和系统公开(公告)号：US06952746B2
公开(公告)日：2005-10-04
申请号：US09881922
申请日：2001-06-14
CPC分类号： G06F11/349
摘要： A method and system for enhancing performance of a bus in a data processing system is described. The method includes monitoring priority of processes in an operating system queue along with data flow through adapters coupled to the bus in a data processing system, determining if increased bus performance is desirable, and adjusting bus parameters to enhance the performance of the bus if increased bus performance is desirable.
摘要翻译： 描述了一种用于增强数据处理系统中总线性能的方法和系统。 该方法包括监视操作系统队列中的进程的优先级以及通过耦合到数据处理系统中的总线的适配器的数据流，确定是否需要增加总线性能，以及调整总线参数以增强总线的性能，如果增加总线 性能是可取的。
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公开(公告)号：US09881099B2
公开(公告)日：2018-01-30
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.
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