公开(公告)号：US11520933B2

公开(公告)日：2022-12-06

申请号：US16726284

申请日：2019-12-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

IPC: G06F21/72 ,  G06F21/62 ,  G06F12/1009

Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

公开(公告)号：US11264063B2

公开(公告)日：2022-03-01

申请号：US16850788

申请日：2020-04-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

IPC: G11C7/12 ,  G11C16/22 ,  G11C7/10 ,  H04L29/06 ,  H04L9/06 ,  H04L9/32

Abstract: A memory device, including a secure command decoder implementing security logic configured to detect commands carrying an encrypted immediate data payload from a requesting host, authenticate the host as source of the command, decode the immediate data and perform a memory access command called for by a command portion of the decrypted immediate data upon the storage cells of the memory device using the non-command portion of the decrypted immediate data, as well as to encrypt any result from executing the command portion prior to returning the result to the requesting host, and an input/output interface for I/O data units supporting multiple hosts.

公开(公告)号：US10969991B2

公开(公告)日：2021-04-06

申请号：US15998456

申请日：2018-08-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

IPC: G06F3/06

Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

公开(公告)号：US20190073300A1

公开(公告)日：2019-03-07

申请号：US16180930

申请日：2018-11-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

IPC: G06F12/06

Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

公开(公告)号：US20170109297A1

公开(公告)日：2017-04-20

申请号：US15215439

申请日：2016-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1663 ,  G06F13/4282

Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

公开(公告)号：US09275695B2

公开(公告)日：2016-03-01

申请号：US14506768

申请日：2014-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/08 ,  G11C7/18 ,  G11C7/06

CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。

公开(公告)号：US12197745B2

公开(公告)日：2025-01-14

申请号：US17817711

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F3/06

Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.

公开(公告)号：US11258599B2

公开(公告)日：2022-02-22

申请号：US16793986

申请日：2020-02-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Chen-Chia Fan

IPC: H04L9/08 ,  H04L9/32 ,  G06F21/62 ,  G06F3/06 ,  G06F12/0877

Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

公开(公告)号：US10809925B2

公开(公告)日：2020-10-20

申请号：US16259268

申请日：2019-01-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Chin-Hung Chang ,  Yu-Chen Wang

IPC: G06F3/06 ,  G06F12/14

Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

公开(公告)号：US20200057575A1

公开(公告)日：2020-02-20

申请号：US15998456

申请日：2018-08-15

Applicant: Macronix International Co., Ltd.

Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

IPC: G06F3/06

Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.