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    Managing tamper detections in secure memory devices
    1.
    发明授权
    Managing tamper detections in secure memory devices 有权

    公开(公告)号：US11487441B2

    公开(公告)日：2022-11-01

    申请号：US16862129

    申请日：2020-04-29

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Feng Cheng

    IPC: G06F3/06 ,  G06F21/86 ,  G06F21/87 ,  G06F21/79 ,  H04Q9/00 ,  G06F12/14 ,  G06Q20/20

    Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing tamper detections in secure memory devices. In one aspect, a secure memory device includes: a memory cell array, one or more tamper detectors each configured to detect a respective type of tamper event on at least part of the secure memory device, and a tamper detection status register storing one or more values each indicating a tamper detection status detected by a corresponding tamper detector. The secure memory device can include a command interface coupled to the tamper detection status register and configured to output the values stored in the tamper detection status register when receiving a trigger. The secure memory device can also include an output pin coupled to the tamper detection status register and be configured to automatically output the values stored in the tamper detection status register via the output pin.

    Security memory scheme
    2.
    发明授权
    Security memory scheme 有权

    公开(公告)号：US11050569B2

    公开(公告)日：2021-06-29

    申请号：US16541009

    申请日：2019-08-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Kuen-Long Chang

    IPC: H04L29/06 ,  H04L9/32 ,  G06F3/06

    Abstract: A memory device can include a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

    I/O bus shared memory system
    3.
    发明授权
    I/O bus shared memory system 有权

    公开(公告)号：US10884956B2

    公开(公告)日：2021-01-05

    申请号：US15215439

    申请日：2016-07-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F13/16 ,  G06F13/42

    Abstract: A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

    Physical unclonable function for security key
    4.
    发明授权
    Physical unclonable function for security key 有权

    公开(公告)号：US10680809B2

    公开(公告)日：2020-06-09

    申请号：US15984685

    申请日：2018-05-21

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F11/30 ,  H04L9/08

    Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.

    Managing secure writes in semiconductor devices
    7.
    发明授权
    Managing secure writes in semiconductor devices 有权

    公开(公告)号：US12086457B2

    公开(公告)日：2024-09-10

    申请号：US17881078

    申请日：2022-08-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

    High performance secure read in secure memory providing a continuous output of encrypted information and specific context
    8.
    发明授权
    High performance secure read in secure memory providing a continuous output of encrypted information and specific context 有权

    公开(公告)号：US11960769B2

    公开(公告)日：2024-04-16

    申请号：US17824226

    申请日：2022-05-25

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

    Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

    MANAGING SECURE WRITES IN SEMICONDUCTOR DEVICES
    9.
    发明公开
    MANAGING SECURE WRITES IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230259301A1

    公开(公告)日：2023-08-17

    申请号：US17881078

    申请日：2022-08-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing secure writes in semiconductor devices. In one aspect, a semiconductor device includes a memory array and logic circuitry coupled to the memory array. The logic circuitry is configured to execute a secure write operation in the memory array in response to receiving encrypted information. The encrypted information includes at least one of information of data to be written, an option code, or multiple addresses in the memory array, the option code specifying a way of writing the data on at least one of the multiple addresses in the memory array.

    Memory chip having security verification function and memory device
    10.
    发明授权
    Memory chip having security verification function and memory device 有权

    公开(公告)号：US11520933B2

    公开(公告)日：2022-12-06

    申请号：US16726284

    申请日：2019-12-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F21/72 ,  G06F21/62 ,  G06F12/1009

    Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

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