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    Length-compatible extended polar codes
    11.
    发明授权
    Length-compatible extended polar codes 有权

    公开(公告)号：US09628114B2

    公开(公告)日：2017-04-18

    申请号：US14794059

    申请日：2015-07-08

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Ming Huang ,  Hsiang-Pang Li ,  Hsie-Chia Chang

    IPC: H03M13/00 ,  H03M13/13 ,  H04L1/00

    CPC classification number: H03M13/616 ,  H03M13/13 ,  H03M13/618 ,  H03M13/635 ,  H04L1/0057 ,  H04L1/0067

    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels.

    Determining read voltages for memory systems
    13.
    发明授权
    Determining read voltages for memory systems 有权

    公开(公告)号：US11631467B2

    公开(公告)日：2023-04-18

    申请号：US17321933

    申请日：2021-05-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Yung-Chun Lee ,  Yu-Ming Huang ,  Han-Wen Hu

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/08

    Abstract: Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.

    MANAGING DATA SECURITY IN STORAGE DEVICES
    14.
    发明申请
    MANAGING DATA SECURITY IN STORAGE DEVICES 有权

    公开(公告)号：US20250165407A1

    公开(公告)日：2025-05-22

    申请号：US18517270

    申请日：2023-11-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Ming Huang ,  Chih-Huai Shih ,  Yung-Chun Li

    IPC: G06F12/14 ,  H04L9/00 ,  H04L9/08

    Abstract: Systems, devices, methods, and circuits for managing data security in storage devices. In one aspect, a storage device includes at least one memory device and a controller coupled to the at least one memory device. The controller is configured to: encrypt first data with a first type of cryptographic algorithm and encrypt second data with a second type of cryptographic algorithm. The first data is associated with a first security level, and the second data is associated with a second security level that is higher than the first security level. The second type of cryptographic algorithm has a greater encryption strength than the first type of cryptographic algorithm.

    Managing error corrections for memory systems
    15.
    发明授权
    Managing error corrections for memory systems 有权

    公开(公告)号：US12153492B1

    公开(公告)日：2024-11-26

    申请号：US18350877

    申请日：2023-07-12

    Applicant: Macronix International Co., Ltd.

    Inventor： Sheng-Han Wu ,  Yu-Ming Huang

    IPC: G06F11/10 ,  G06F11/20

    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing error corrections for memory systems are provided. In one aspect, a memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to: read data from a data page of the memory, perform a first phase Error-Correcting Code (ECC) test on the read data based on first ECC data associated with the data, and in response to determining that the read data fails to pass the first phase ECC test, perform a second phase ECC test on a portion of the read data based on second ECC data. The first ECC data is stored together with the data in the data page. The second ECC data is associated with a portion of the data corresponding to the portion of the read data, and stored in a redundancy page different from the data page.

    DETERMINING READ VOLTAGES FOR MEMORY SYSTEMS
    16.
    发明公开
    DETERMINING READ VOLTAGES FOR MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20230153198A1

    公开(公告)日：2023-05-18

    申请号：US17528346

    申请日：2021-11-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Ming Huang ,  Yung-Chun Li

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1016 ,  G06F3/0655 ,  G06F3/0625 ,  G06F3/0679 ,  G06F2201/805

    Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.

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