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    Memory system for maintaining data consistency and operation method thereof
    1.
    发明授权
    Memory system for maintaining data consistency and operation method thereof 有权

    公开(公告)号：US11704246B2

    公开(公告)日：2023-07-18

    申请号：US17539257

    申请日：2021-12-01

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Bo-Rong Lin ,  Ming-Liang Wei ,  Hsiang-Pang Li ,  Nai-Jia Dong ,  Hsiang-Yun Cheng ,  Chia-Lin Yang

    IPC: G06F12/0804

    CPC classification number: G06F12/0804 ,  G06F2212/601

    Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

    Stress trim and modified ISPP procedures for PCM
    6.
    发明授权
    Stress trim and modified ISPP procedures for PCM 有权
    PCM的应力修剪和修改的ISPP程序

    公开(公告)号：US09564216B2

    公开(公告)日：2017-02-07

    申请号：US14682903

    申请日：2015-04-09

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Win-San Khwa ,  Tzu-Hsiang Su ,  Chao-I Wu ,  Hsiang-Pang Li

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  G11C29/04

    CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0064 ,  G11C29/028 ,  G11C29/06 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0066 ,  G11C2013/0083 ,  G11C2029/0409

    Abstract: A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.

    Abstract translation: 描述了包括包括多个块的存储器单元的阵列的存储器电路。 该电路包括控制器，该控制器包括用于对多个块中的选定块执行程序序列的逻辑。 程序序列包括程序/验证周期的模式。 该电路包括用于将不同模式的程序/验证周期分配给多个块中的不同块的逻辑。 电路包括用于改变分配给多个块中的特定块的特定模式的逻辑。 该电路包括用于维护多个块中的块的统计信息的逻辑，关于分配给块的编程/验证周期的模式的块中的小区的性能。 控制器包括将应力序列应用于所选择的块之一的逻辑，应力序列包括施加到所选块中的一个存储单元的应力脉冲。

    DATA PROCESSING METHOD AND SYSTEM WITH APPLICATION-LEVEL INFORMATION AWARENESS
    7.
    发明申请
    DATA PROCESSING METHOD AND SYSTEM WITH APPLICATION-LEVEL INFORMATION AWARENESS 有权
    具有应用级信息意识的数据处理方法和系统

    公开(公告)号：US20160154674A1

    公开(公告)日：2016-06-02

    申请号：US14696657

    申请日：2015-04-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ye-Jyun Lin ,  Hsiang-Pang Li ,  Shang-Xuan Zou ,  Chia-Lin Yang

    IPC: G06F9/48 ,  G06F9/455 ,  G06F9/54

    CPC classification number: G06F9/4881 ,  G06F9/4812

    Abstract: A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.

    Abstract translation: 数据处理系统包括存储设备，接口模块和调度器。 接口模块被配置为经由第一数据路径分派非优先化请求，并且经由第二数据路径传送应用的应用级信息。 耦合到第一和第二数据路径的调度器被配置为使得能够根据从第一和第二数据路径分别接收的非优先级请求和应用级信息来访问存储设备。

    Memory disturb reduction for nonvolatile memory
    8.
    发明授权
    Memory disturb reduction for nonvolatile memory 有权
    非易失性存储器的存储器干扰减少

    公开(公告)号：US09025375B2

    公开(公告)日：2015-05-05

    申请号：US14060296

    申请日：2013-10-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G11C16/04 ,  G11C16/34 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

    Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

    Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

    Management system for managing memory device and management method for managing the same
    9.
    发明授权
    Management system for managing memory device and management method for managing the same 审中-公开

    公开(公告)号：US10671296B2

    公开(公告)日：2020-06-02

    申请号：US15672430

    申请日：2017-08-09

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G06F3/06 ,  G06F12/02 ,  G11C7/04

    Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

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