公开(公告)号：US12255734B2

公开(公告)日：2025-03-18

申请号：US17973575

申请日：2022-10-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Avi Urman ,  Natan Manevich

IPC: H04J3/06

Abstract: In one embodiment, a system includes a network interface controller including a device interface to connect to a processing device and receive a time synchronization marker message from an application running on the processing device, a network interface to send packets over a network, and packet processing circuitry to process the time synchronization marker message for sending via the network interface over the network to a slave clock device, generate a time synchronization follow-up message including a timestamp indicative of when the synchronization marker message egressed the network interface, and process the time synchronization follow-up message for sending via the network interface over the network to the slave clock device.

公开(公告)号：US20250021130A1

公开(公告)日：2025-01-16

申请号：US18349976

申请日：2023-07-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciej Machnikowski

IPC: G06F1/12

Abstract: In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.

公开(公告)号：US12177325B2

公开(公告)日：2024-12-24

申请号：US18523991

申请日：2023-11-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

公开(公告)号：US12079029B2

公开(公告)日：2024-09-03

申请号：US17313026

申请日：2021-05-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Itai Levy ,  Dotan David Levi ,  Nir Nitzani ,  Natan Manevich ,  Alex Vaynman ,  Ariel Almog

IPC: G06F1/12 ,  G06F13/20 ,  H04L7/00

CPC classification number: G06F1/12 ,  G06F13/20 ,  H04L7/0012

Abstract: A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.

公开(公告)号：US20240281292A1

公开(公告)日：2024-08-22

申请号：US18110788

申请日：2023-02-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Shay Aisman ,  Ariel Almog ,  Eliel Peretz ,  Igor Voks

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/505

Abstract: A device includes a transceiver coupled to a processing device. The processing device is to determine a first time for executing an operation associated with a work execution agent of a plurality of work execution agent. The processing device is further to receive a latency measurement associated with the work execution agent responsive to transmitting the request. The latency measurement is calculated after executing a previous operation associated with the work execution agent at the device. The processing device is also to modify the first time to a second time for executing the operation responsive to receiving the latency measurement.

公开(公告)号：US20240134731A1

公开(公告)日：2024-04-25

申请号：US18074751

申请日：2022-12-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Shay Aisman ,  Ariel Almog ,  Ran Avraham Koren

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0736

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

公开(公告)号：US11835999B2

公开(公告)日：2023-12-05

申请号：US17578115

申请日：2022-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F13/4022 ,  G06F2213/3808

Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.

公开(公告)号：US20230362096A1

公开(公告)日：2023-11-09

申请号：US18106953

申请日：2023-02-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Roee Moyal

IPC: H04L47/22 ,  H04L47/263

CPC classification number: H04L47/225 ,  H04L47/263

Abstract: A system includes a device coupled to a processing device. The processing device is to receive a request to execute a plurality of workloads, the request comprising a rate to execute each workload of the plurality of workloads and a parameter value indicating an execution offset. The processing device is further to determine a sequence for executing the plurality of workloads based on receiving the rate and the parameter value, where the sequence is to execute each workload at the respective rate and each workload of the plurality of workloads is executed at a different time based on the parameter value. The processing device is to execute the plurality of workloads in accordance with the sequence upon determining the sequence to execute the plurality of workloads.

公开(公告)号：US20230251899A1

公开(公告)日：2023-08-10

申请号：US17667600

申请日：2022-02-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Natan Manevich ,  Wojciech Wasko ,  Igor Voks

IPC: G06F9/48

CPC classification number: G06F9/4887

Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.

公开(公告)号：US20230229188A1

公开(公告)日：2023-07-20

申请号：US17578115

申请日：2022-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen

IPC: G06F1/10 ,  G06F13/40

CPC classification number: G06F1/10 ,  G06F13/4022 ,  G06F2213/3808

Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.