Abstract:
Electronic apparatus includes a laminated multi-layer circuit substrate, including first and second rigid cards and a flexible section between the first and second rigid cards. First and second sets of electrical terminals are disposed respectively on the first and second rigid cards and arranged to mate with respective bus connectors configured in accordance with a predefined bus standard. At least one bus interface circuit is configured to communicate over a bus in accordance with the predefined bus standard and disposed on the first rigid card. Printed conductors run continuously from the first rigid card, over the flexible section of the substrate, to the second rigid card and connect the at least one bus interface circuit on the first rigid card to the second set of electrical terminals on the second rigid card.
Abstract:
A network adapter includes one or more ports and circuitry. The one or more ports are configured to connect to a communication network. The circuitry is coupled to a network node that includes multiple hosts, and is configured to exchange management packets between a control server and a Baseboard Management Controller (BMC) that runs at least first and second BMC instances that share a single MAC address and are associated respectively with first and second hosts, and to exchange, over the communication network via the one or more ports, data packets between the hosts and one or more remote nodes.
Abstract:
Computerized methods and systems are disclosed for configuring a network controller (NC). These methods and systems recognize, via a network device, e.g., hardware, software, processors, storage media, memory, a predetermined command from a management controller (MC). The network device responds to the predetermined command by configuring the NC with a message type associated with an event, and controlling enablement of a message associated with the message type using a selectable enable bit as defined in the predetermined command.
Abstract:
In one embodiment, a secure challenge-response method includes requesting respective token challenges from devices, receiving the respective token challenges from the devices, providing the respective token challenges to a signing server, receiving from the signing server a signature of the respective token challenges signed with a private key of the signing server, and providing to a given device of the devices a request to perform an operation, the request including the signature and the respective token challenges.
Abstract:
A compute node includes a network-connected device, and a baseboard management controller (BMC) that is connected to the network-connected device by a sideband interface. The network-connected device is configured to communicate with a network. The BMC is configured to configure the network-connected device, via the sideband interface, to engage in a debug session over the network with a remote debug device.
Abstract:
Apparatus having a firmware memory storing firmware, a cache memory loading at least part of the firmware for execution by a processor, and a firmware checking engine having a defined syndrome storage location and performing the following iteratively on cache line entries associated with the firmware stored in the cache memory: choose a cache line entry; verify that an address mapped in the cache line entry maps to an address in the firmware memory, and when the cache line entry is locked and the address mapped in the cache line entry maps to an address in the firmware memory, compare a content of the cache line entry to a content of a corresponding address in the firmware stored in the firmware memory, and produce an integrity result indicating whether integrity of the apparatus has been compromised.
Abstract:
Apparatus having a firmware memory storing firmware, a cache memory loading at least part of the firmware for execution by a processor, and a firmware checking engine having a defined syndrome storage location and performing the following iteratively on cache line entries associated with the firmware stored in the cache memory: choose a cache line entry; verify that an address mapped in the cache line entry maps to an address in the firmware memory, and when the cache line entry is locked and the address mapped in the cache line entry maps to an address in the firmware memory, compare a content of the cache line entry to a content of a corresponding address in the firmware stored in the firmware memory, and produce an integrity result indicating whether integrity of the apparatus has been compromised. The abstract is not meant to be limiting.
Abstract:
A host computer connects to a data network via a host interface to a network interface controller A sideband interface connects the network interface controller to a baseboard management controller having a management network port for connection to a management network. A path is established in the network interface controller between the host interface the basement management controller via the sideband interface of the network interface controller to conduct data selectively between the management network and either the host central processing unit and the or internally in the network interface controller.
Abstract:
A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that support a management protocol and belong to a multi-CPU device, and with a Baseboard Management Controller (BMC). The processor is configured to, in response to a request to enumerate the bus interfaces that support the management protocol, report support of the management protocol over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device, and exchange management packets over the communication network between the BMC and a remote management computer, wherein the management packets manage the entire multi-CPU device but traverse only the single selected bus interface.
Abstract:
A network adapter includes one or more network ports, multiple bus interfaces, and a processor. The one or more network ports are configured to communicate with a communication network. The multiple bus interfaces are configured to communicate with multiple respective Central Processing Units (CPUs) that belong to a multi-CPU device. The processor is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, and, in response to a request from the multi-CPU device to report the support of the Option-ROM functionality, to report the support of the Option-ROM functionality over only a single bus interface, selected from among the multiple bus interfaces connecting the network adapter to the multi-CPU device.