公开(公告)号：US11816357B2

公开(公告)日：2023-11-14

申请号：US17400914

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G06F3/00 ,  G06F3/06 ,  G11C5/14

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C5/147

Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

公开(公告)号：US11804257B2

公开(公告)日：2023-10-31

申请号：US17992726

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/40 ,  G11C11/4074 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/525 ,  G11C11/22 ,  G06F13/16

CPC classification number: G11C11/4074 ,  G06F13/1668 ,  G11C11/2297 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/1427 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

公开(公告)号：US20230048317A1

公开(公告)日：2023-02-16

申请号：US17400886

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/4074 ,  H01L25/065 ,  H01L23/00

Abstract: Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.

公开(公告)号：US11488651B2

公开(公告)日：2022-11-01

申请号：US17135403

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/403 ,  G11C11/408

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US11264075B2

公开(公告)日：2022-03-01

申请号：US16160801

申请日：2018-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US10885967B2

公开(公告)日：2021-01-05

申请号：US16247277

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/403

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.

公开(公告)号：US09047978B2

公开(公告)日：2015-06-02

申请号：US14010120

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract translation: 本文公开了用于选择行刷新的装置和方法。 示例性装置可以包括刷新控制电路。 刷新控制电路可以被配置为从地址总线接收与目标多个存储器单元相关联的目标地址。 刷新控制电路还可以被配置为至少部分地响应于确定已经发生了多个刷新操作来向地址总线提供邻近地址。 在一些示例中，与邻近地址相关联的多个存储单元可以是与目标多个存储单元相邻的多个存储单元。

公开(公告)号：US20230090919A1

公开(公告)日：2023-03-23

申请号：US17992726

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/4074 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/525 ,  G11C11/22 ,  G06F13/16

Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

公开(公告)号：US20230046912A1

公开(公告)日：2023-02-16

申请号：US17400914

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G06F3/06

Abstract: Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

公开(公告)号：US20210118490A1

公开(公告)日：2021-04-22

申请号：US17135403

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Debra M. Bell ,  George B. Raad ,  Brian P. Callaway ,  Joshua E. Alzheimer

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/403

Abstract: A memory device may include a phase driver circuit that may output a first voltage for refreshing a plurality of memory cells. The memory device may also include a plurality of word line driver circuits that may receive the first voltage via the phase driver circuit, such that each word line driver circuit of the plurality of word line driver circuits may provide the first voltage to a respective word line associated with a respective portion of the plurality of memory cells. In addition, each word line driver circuit may refresh the respective portion of the plurality of memory cells based on a respective word line enable signal provided to a first switch of the respective word line driver circuit.