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公开(公告)号:US09748311B2
公开(公告)日:2017-08-29
申请号:US14535731
申请日:2014-11-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Paolo Fantini , Cristina Casellato , Fabio Pellizzer
IPC: H01L45/00 , H01L27/24 , H01L27/115 , H01L21/764 , H01L21/768 , H01L27/11521 , H01L27/11524 , H01L21/762 , H01L27/1157
CPC classification number: H01L27/2463 , H01L21/76224 , H01L21/764 , H01L21/7682 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1157 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1675
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
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公开(公告)号:US20160133671A1
公开(公告)日:2016-05-12
申请号:US14535731
申请日:2014-11-07
Applicant: Micron Technology, Inc.
Inventor: Paolo Fantini , Cristina Casellato , Fabio Pellizzer
CPC classification number: H01L27/2463 , H01L21/76224 , H01L21/764 , H01L21/7682 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1157 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L45/1675
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
Abstract translation: 交叉点存储器阵列包括多个可变电阻存储器单元柱。 相邻的记忆单元柱由包括埋入空隙的部分填充的间隙分开。 此外,相邻的存储单元柱包括至少部分地被埋入空隙插入的存储材料元件。
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公开(公告)号:US20150357563A1
公开(公告)日:2015-12-10
申请号:US14828050
申请日:2015-08-17
Applicant: Micron Technology, Inc.
Inventor: Fabio Pellizzer , Michele Magistretti , Cristina Casellato , Monica Vigilante
CPC classification number: H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1608 , H01L45/1675
Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.
Abstract translation: 描述了制造相变存储单元的方法。 该方法包括在衬底上的金属层(226)上形成介电层(228)。 在介电层上形成相变材料层(230)。 通过分解介电层的一部分,在介电层内形成接触区域(232),位于相变材料层和金属层之间。
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公开(公告)号:US20150243708A1
公开(公告)日:2015-08-27
申请号:US14189490
申请日:2014-02-25
Applicant: MICRON TECHNOLOGY, INC
Inventor: Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
Abstract translation: 所公开的技术通常涉及集成电路器件,特别涉及交叉点存储器阵列及其制造方法。 在一个方面,一种制造交叉点存储器阵列的方法包括形成存储单元材料堆,所述存储单元材料堆在第一活性材料上包括第一活性材料和第二活性材料,其中第一和第二活性材料之一包括存储材料 并且第一和第二活性材料中的另一个包括选择材料。 制造交叉点阵列的方法还包括对存储单元材料堆叠进行图案化,其包括通过存储单元材料堆叠的第一和第二活性材料中的至少一个的蚀刻,在至少一个的至少一个的侧壁上形成保护衬垫 在蚀刻通过第一和第二活性材料之一之后蚀刻第一和第二活性材料,并且在第一和第二活性材料之一的侧壁上形成保护衬垫之后进一步蚀刻存储单元材料堆叠。
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公开(公告)号:US09570681B2
公开(公告)日:2017-02-14
申请号:US14491713
申请日:2014-09-19
Applicant: Micron Technology, Inc.
Inventor: Cristina Casellato , Carmela Cupeta , Michele Magistretti , Fabio Pellizzer , Roberto Somaschini
IPC: H01L45/00 , H01L23/528 , H01L27/24 , H01L23/532 , H01L27/10
CPC classification number: H01L45/16 , H01L23/5283 , H01L23/53295 , H01L27/101 , H01L27/24 , H01L27/2436 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L2924/0002 , H01L2924/00
Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
Abstract translation: 电阻随机存取存储器可以包括存储器阵列和围绕存储器阵列的周边。 外围的解码器可以通过使用相同的金属沉积在同一时间在周边和阵列中形成金属化而耦合到阵列中的地址线。 金属化可以在阵列中形成行线。
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公开(公告)号:US20150044832A1
公开(公告)日:2015-02-12
申请号:US14491713
申请日:2014-09-19
Applicant: Micron Technology, Inc.
Inventor: Cristina Casellato , Carmela Cupeta , Michele Magistretti , Fabio Pellizzer , Roberto Somaschini
IPC: H01L45/00 , H01L23/528 , H01L27/24
CPC classification number: H01L45/16 , H01L23/5283 , H01L23/53295 , H01L27/101 , H01L27/24 , H01L27/2436 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L2924/0002 , H01L2924/00
Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
Abstract translation: 电阻随机存取存储器可以包括存储器阵列和围绕存储器阵列的周边。 外围的解码器可以通过使用相同的金属沉积在同一时间在周边和阵列中形成金属化而耦合到阵列中的地址线。 金属化可以在阵列中形成行线。
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