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公开(公告)号：US11600665B2
公开(公告)日：2023-03-07
申请号：US17069347
申请日：2020-10-13
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US20180358411A1
公开(公告)日：2018-12-13
申请号：US16045516
申请日：2018-07-25
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Cristina Casellato , Fabio Pellizzer
IPC: H01L27/24 , H01L27/115 , H01L27/1157 , H01L21/762 , H01L27/11524 , H01L21/768 , H01L27/11521 , H01L45/00 , H01L21/764
CPC classification number: H01L27/2463 , H01L21/76224 , H01L21/764 , H01L21/7682 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1157 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/141 , H01L45/144 , H01L45/1675
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
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公开(公告)号：US20170358628A1
公开(公告)日：2017-12-14
申请号：US15688027
申请日：2017-08-28
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Cristina Casellato , Fabio Pellizzer
IPC: H01L27/24 , H01L45/00 , H01L21/764 , H01L27/115 , H01L27/1157 , H01L21/768 , H01L21/762 , H01L27/11524 , H01L27/11521
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
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公开(公告)号：US10854674B2
公开(公告)日：2020-12-01
申请号：US15693102
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US10396125B2
公开(公告)日：2019-08-27
申请号：US16045516
申请日：2018-07-25
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Cristina Casellato , Fabio Pellizzer
IPC: H01L21/762 , H01L21/764 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1157 , H01L45/00 , H01L27/24
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
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Patent Agency Ranking
公开(公告)号：US20170365642A1
公开(公告)日：2017-12-21
申请号：US15693102
申请日：2017-08-31
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US10680037B2
公开(公告)日：2020-06-09
申请号：US15688027
申请日：2017-08-28
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Cristina Casellato , Fabio Pellizzer
IPC: H01L21/764 , H01L21/762 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1157 , H01L27/24 , H01L45/00
Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
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公开(公告)号：US20190006421A1
公开(公告)日：2019-01-03
申请号：US16113631
申请日：2018-08-27
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Michele Magistretti , Cristina Casellato , Monica Vigilante
Abstract: A method for fabricating a phase-change memory cell is described. The method includes forming a dielectric layer (228) on a metal layer (226) above a substrate. A phase-change material layer (230) is formed on the dielectric layer. A contact region (232) is formed, within the dielectric layer, between the phase-change material layer and the metal layer by breaking-down a portion of the dielectric layer.
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公开(公告)号：US09806129B2
公开(公告)日：2017-10-31
申请号：US14189490
申请日：2014-02-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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公开(公告)号：US20210091140A1
公开(公告)日：2021-03-25
申请号：US17069347
申请日：2020-10-13
Applicant: Micron Technology, Inc.
Inventor： Marcello Ravasio , Samuele Sciarrillo , Fabio Pellizzer , Innocenzo Tortorelli , Roberto Somaschini , Cristina Casellato , Riccardo Mottadelli
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.
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