公开(公告)号：US10825485B2

公开(公告)日：2020-11-03

申请号：US16439628

申请日：2019-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C8/00 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus is disclosed. The apparatus comprises a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US10725913B2

公开(公告)日：2020-07-28

申请号：US15977808

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F12/0806 ,  H04L5/00 ,  H04L27/14

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

公开(公告)号：US10424351B2

公开(公告)日：2019-09-24

申请号：US16222806

申请日：2018-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US10355893B2

公开(公告)日：2019-07-16

申请号：US15977813

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: H04L27/04 ,  G06F12/02 ,  G11C8/12 ,  G06F13/38 ,  H04L27/06 ,  H04L27/02 ,  H04L25/49 ,  G06F13/16 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US20190103149A1

公开(公告)日：2019-04-04

申请号：US15977820

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C8/12 ,  G06F12/02

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

公开(公告)号：US10157647B2

公开(公告)日：2018-12-18

申请号：US15933167

申请日：2018-03-22

Applicant: Micron Technology, Inc.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/00 ,  G11C7/10

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US20180130508A1

公开(公告)日：2018-05-10

申请号：US15855849

申请日：2017-12-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C7/10 ,  G11C8/08 ,  G11C7/12

CPC classification number: G11C5/14 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US09911469B1

公开(公告)日：2018-03-06

申请号：US15348578

申请日：2016-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Dean D. Gans ,  Larren G. Weber

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C5/14 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first operating mode and to selectively provide a second supply voltage to the output node in a second operating mode, based on one or more enable signals.

公开(公告)号：US20230238038A1

公开(公告)日：2023-07-27

申请号：US18157945

申请日：2023-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Daniel C. Skinner

IPC: G11C7/10

CPC classification number: G11C7/1045 ,  G11C7/109

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

公开(公告)号：US11698726B2

公开(公告)日：2023-07-11

申请号：US17645101

申请日：2021-12-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  Shunichi Saito

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F12/10 ,  G06F2212/1012

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.