公开(公告)号：US09558799B2

公开(公告)日：2017-01-31

申请号：US14954587

申请日：2015-11-30

Applicant: Micron Technology, Inc.

Inventor： Marco Ferrario ,  Christophe Vincent Antoine Laurent ,  Francesco Mastroianni

IPC: G11C8/12 ,  G11C13/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/21 ,  G06F12/08 ,  G11C16/04

CPC classification number: G11C8/12 ,  G06F12/0802 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/22 ,  G11C8/18 ,  G11C11/21 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/04

Abstract: A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.

Abstract translation: 存储器件包括具有从行地址缓冲器提供上行地址的相位的操作，将上行地址与下行地址组合以选择行数据缓冲器的数据的相位和输出数据的相位 从行数据缓冲器，其中激活命令开始并且随后的激活命令被忽略，直到经过预设时间。