公开(公告)号：US11545199B2

公开(公告)日：2023-01-03

申请号：US17200233

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US20210280267A1

公开(公告)日：2021-09-09

申请号：US16811691

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  John E. Riley

IPC: G11C29/44 ,  G11C29/38 ,  G11C17/16 ,  G11C17/18

Abstract: Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.

公开(公告)号：US10950282B2

公开(公告)日：2021-03-16

申请号：US16540011

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US10424356B2

公开(公告)日：2019-09-24

申请号：US16047954

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US10318238B2

公开(公告)日：2019-06-11

申请号：US16107867

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US20180357041A1

公开(公告)日：2018-12-13

申请号：US16107867

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

CPC classification number: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US09778903B2

公开(公告)日：2017-10-03

申请号：US14573215

申请日：2014-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

CPC classification number: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

公开(公告)号：US11670356B2

公开(公告)日：2023-06-06

申请号：US17305878

申请日：2021-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshinori Fujiwara ,  Harish V. Gadamsetty ,  Gary Howe ,  Dennis G. Montierth ,  Michael A. Shore ,  Jason M. Johnson

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12

CPC classification number: G11C11/40622 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/4401 ,  G11C29/787 ,  G11C2029/1202

Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).

公开(公告)号：US11646095B2

公开(公告)日：2023-05-09

申请号：US16811691

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  John E. Riley

IPC: G11C29/44 ,  G11C17/18 ,  G11C17/16 ,  G11C29/38 ,  G11C29/54

CPC classification number: G11C29/4401 ,  G11C17/16 ,  G11C17/18 ,  G11C29/38

Abstract: Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.

公开(公告)号：US11099774B2

公开(公告)日：2021-08-24

申请号：US15691447

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Gary Howe

IPC: G06F3/00 ,  G11C11/00 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/12

Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.