公开(公告)号：US20240420746A1

公开(公告)日：2024-12-19

申请号：US18814826

申请日：2024-08-26

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US20220391334A1

公开(公告)日：2022-12-08

申请号：US17882550

申请日：2022-08-06

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Vaughn N. Johnson ,  Kyle Alexander ,  Gary L. Howe ,  Brian T. Pecha ,  Miles S. Wiscombe

IPC: G06F13/16 ,  G11C11/406 ,  G11C11/4096

Abstract: Memory devices and systems with improved command/address bus utilization are disclosed herein. In one embodiment, a memory device comprises a plurality of external command/address terminals and a command decoder. The plurality of external command/address terminals are configured to receive a command as a corresponding plurality of command/address bits. A first set of the command/address bits indicate a read or write operation. A second set of the command/address bits indicate whether to execute a refresh operation. The memory device is configured to, in response to the first set of command/address bits, execute the read or write operation on a portion of a memory array. The memory device is further configured to, in response to the second set of command/address bits, execute the refresh operation to refresh at least one memory bank of the memory array when the second set of command/address bits indicate that the refresh operation should be executed.

公开(公告)号：US20220262413A1

公开(公告)日：2022-08-18

申请号：US17178475

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Gary L. Howe

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4093

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

公开(公告)号：US20220147131A1

公开(公告)日：2022-05-12

申请号：US17094579

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Gary L. Howe ,  Miles S. Wiscombe ,  Eric J. Stave

IPC: G06F1/3203 ,  G11C11/4074

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

公开(公告)号：US20210241805A1

公开(公告)日：2021-08-05

申请号：US16779866

申请日：2020-02-03

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

公开(公告)号：US20210173770A1

公开(公告)日：2021-06-10

申请号：US17181718

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G06F12/02 ,  G06F12/0855 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

公开(公告)号：US10929023B2

公开(公告)日：2021-02-23

申请号：US16541764

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US10892006B1

公开(公告)日：2021-01-12

申请号：US16786661

申请日：2020-02-10

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Gary L. Howe

IPC: G11C11/40 ,  G11C11/4096 ,  G11C11/4076

Abstract: A memory device include write leveling circuitry that is configured to receive a write command from the command interface. The write leveling circuitry also receives a data strobe (DQS) signal from a host device (e.g., processor) and receives a clock signal from the host device. The write leveling circuitry also compares phases of the DQS signal and the clock signal using a phase detector. The write leveling circuitry also generates an internal write signal (IWS) based upon the write command, and outputs a captured result of a write leveling operation based at least in part on the compared phases and the IWS.

公开(公告)号：US10832760B2

公开(公告)日：2020-11-10

申请号：US16690598

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  David R. Brown ,  Gary L. Howe

IPC: G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4076

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

公开(公告)号：US10824503B2

公开(公告)日：2020-11-03

申请号：US15812949

申请日：2017-11-14

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/4063 ,  G11C11/4076 ,  G11C29/52 ,  G11C7/22 ,  G11C7/10 ,  G11C29/04 ,  G11C8/12

Abstract: A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.