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公开(公告)号：US12068034B2
公开(公告)日：2024-08-20
申请号：US17899409
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Giovanni Maria Paolucci , Dave Scott Ebsen , James Fitzpatrick , Akira Goda , Jeffrey S. McNeil , Umberto Siciliani , Daniel J. Hubbard , Walter Di Francesco , Michele Incarnati
CPC classification number: G11C16/102 , G11C16/08 , G11C16/3404
Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
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公开(公告)号：US20240069792A1
公开(公告)日：2024-02-29
申请号：US18228065
申请日：2023-07-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Maria Paolucci
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A memory device includes a memory array and control logic to perform operations including identifying a target cell and a set of cells adjacent to the target cell. Each cell of the set of cells is associated with a respective adjacent cell state. The operations further include determining, for each adjacent cell state, a respective interference value, assigning, based on the respective interference value, each adjacent cell state to a respective bin of a set of state information bins, and in response to determining that each bin of the set of state information bins has at least one adjacent cell state assigned to it, and determining a set of read level offsets for reading the target cell. Each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.
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公开(公告)号：US20220271127A1
公开(公告)日：2022-08-25
申请号：US17182737
申请日：2021-02-23
Applicant: Micron Technology, Inc.
Inventor： Ramanathan Gandhi , Augusto Benvenuti , Giovanni Maria Paolucci
IPC: H01L29/10 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/788 , H01L29/792
Abstract: A transistor comprises a channel region having a frontside and a backside. The channel region comprises a frontside channel material at the frontside and a backside channel material at the backside. A gate is adjacent the frontside of the channel region, with a gate insulator being between the gate and the channel region. The frontside channel material has total n-type dopant therein of greater than 1×1018 atoms/cm3 to no greater than 1×1020 atoms/cm3. The backside channel material has total n-type dopant therein of 0 atoms/cm3 to 1×1018 atoms/cm3. Other embodiments and aspects are disclosed.
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公开(公告)号：US20210233591A1
公开(公告)日：2021-07-29
申请号：US17228807
申请日：2021-04-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.
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Patent Agency Ranking
公开(公告)号：US12190961B2
公开(公告)日：2025-01-07
申请号：US17988090
申请日：2022-11-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.
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16.发明公开公开(公告)号：US20230360705A1
公开(公告)日：2023-11-09
申请号：US18138551
申请日：2023-04-24
Applicant: Micron Technology, Inc.
Inventor： Huai-Yuan Tseng , Giovanni Maria Paolucci , Kishore Kumar Muchherla , James Fitzpatrick , Akira Goda
Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.
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公开(公告)号：US20230078036A1
公开(公告)日：2023-03-16
申请号：US17988090
申请日：2022-11-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.
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公开(公告)号：US20220271142A1
公开(公告)日：2022-08-25
申请号：US17182808
申请日：2021-02-23
Applicant: Micron Technology, Inc.
Inventor： Ramanathan Gandhi , Augusto Benvenuti , Giovanni Maria Paolucci
IPC: H01L29/51
Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.
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公开(公告)号：US20210065810A1
公开(公告)日：2021-03-04
申请号：US16555050
申请日：2019-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.
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