公开(公告)号：US20250140324A1

公开(公告)日：2025-05-01

申请号：US19010407

申请日：2025-01-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Memories having a controller configured to increase a voltage level applied to a data line and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells during a first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate in response to an end of the first period of time, and ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor in response to the voltage level applied to the data line reaching a predetermined voltage level.

公开(公告)号：US20250140323A1

公开(公告)日：2025-05-01

申请号：US18781524

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Kishore K. Muchherla ,  Hong Lu ,  Akira Goda ,  Shyam Sunder Raghunathan ,  Peter Feeley ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.

公开(公告)号：US11514987B2

公开(公告)日：2022-11-29

申请号：US17228807

申请日：2021-04-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

公开(公告)号：US20240357815A1

公开(公告)日：2024-10-24

申请号：US18637127

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Paolo Tessariol ,  Enrico Varesi ,  Emilio Camerlenghi ,  Stephen W. Russell ,  Yoshiaki Fukuzumi

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: Methods, systems, and devices for methods to increase cell density using a lateral etch are described. A process to manufacture a memory array may include a lateral wet etch to split a pillar into two stacks of memory cells. In some cases, the manufacturing process may include forming a trench in a vertical stack of layers and forming a memory cell pillar which includes an oxide material, a semiconductor channel material, and an insulating material in the trench. Sidewalls of the pillar may be laterally etched to remove portions of the oxide material and the semiconductor material, which may form two stacks of memory cells, each stack in contact with opposing sidewalls of the trench. In some examples, the manufacturing process may include forming one or more supportive piers within the trench, and the pillar of memory cell material may be formed between pairs of piers.

公开(公告)号：US20210343640A1

公开(公告)日：2021-11-04

申请号：US17374634

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US20210233591A1

公开(公告)日：2021-07-29

申请号：US17228807

申请日：2021-04-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

公开(公告)号：US20210202020A1

公开(公告)日：2021-07-01

申请号：US17202398

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Tecla Ghilardi ,  Tommaso Vali ,  Emilio Camerlenghi ,  William C. Filipiak ,  Andrea D'Alessandro

IPC: G11C16/34 ,  G11C16/26 ,  G11C8/08 ,  G11C11/413 ,  G11C5/06

Abstract: Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.

公开(公告)号：US10756105B2

公开(公告)日：2020-08-25

申请号：US16200158

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  M. Jared Barclay ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28

Abstract: A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.

公开(公告)号：US20220059559A1

公开(公告)日：2022-02-24

申请号：US17000754

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Umberto Maria Meotto ,  Emilio Camerlenghi ,  Paolo Tessariol ,  Luca Laurin

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/544

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

公开(公告)号：US11011236B2

公开(公告)日：2021-05-18

申请号：US16555050

申请日：2019-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/30 ,  G11C16/04 ,  G11C16/24

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.