公开(公告)号：US20190067475A1

公开(公告)日：2019-02-28

申请号：US16110217

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L21/425

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

公开(公告)号：US10170194B1

公开(公告)日：2019-01-01

申请号：US15692712

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.

公开(公告)号：US20180226427A1

公开(公告)日：2018-08-09

申请号：US15945215

申请日：2018-04-04

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20170317099A1

公开(公告)日：2017-11-02

申请号：US15651916

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US11527620B2

公开(公告)日：2022-12-13

申请号：US17317668

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US20220181341A1

公开(公告)日：2022-06-09

申请号：US17110439

申请日：2020-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Michael Violette ,  Mark A. Helm ,  Guangyu Huang ,  Vladimir Mikhalev

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  G11C16/04

Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.

公开(公告)号：US20210384354A1

公开(公告)日：2021-12-09

申请号：US16891462

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11529

Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

公开(公告)号：US20210265467A1

公开(公告)日：2021-08-26

申请号：US17317668

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US10777281B2

公开(公告)日：2020-09-15

申请号：US16227874

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529 ,  G11C16/16 ,  H01L27/11565 ,  H01L27/11575 ,  G11C7/10

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.

公开(公告)号：US20200287003A1

公开(公告)日：2020-09-10

申请号：US16294759

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L29/16 ,  H01L29/207 ,  H01L29/08 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.