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    Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor
    13.
    发明申请
    Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor 审中-公开

    公开(公告)号：US20180075165A1

    公开(公告)日：2018-03-15

    申请号：US15806073

    申请日：2017-11-07

    Applicant: Micron Technology Inc.

    Inventor： Harold B. Noyes ,  David R. Brown

    IPC: G06F17/30 ,  G06F11/30

    Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.

    METHODS AND SYSTEMS TO ACCOMPLISH VARIABLE WIDTH DATA INPUT
    15.
    发明申请
    METHODS AND SYSTEMS TO ACCOMPLISH VARIABLE WIDTH DATA INPUT 有权
    实现可变宽度数据输入的方法和系统

    公开(公告)号：US20140223044A1

    公开(公告)日：2014-08-07

    申请号：US14245703

    申请日：2014-04-04

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes

    IPC: G06F13/38

    CPC classification number: G06F13/385 ,  G06F13/4018

    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.

    Abstract translation: 公开了用于将可变宽度数据输入到模式识别处理器的方法和系统。 可变宽度数据输入方法可以包括通过具有第一宽度的数据总线接收字节，并且接收指示一个或多个字节中的每一个的有效性的一个或多个信号。 有效字节可以顺序地提供给8位宽数据流中的模式识别处理器。 在一个实施例中，系统可以包括一个或多个地址线，其被配置为提供指示通过数据总线传送的字节的有效性的一个或多个信号。 系统可以包括缓冲器和控制逻辑以顺序地处理有效字节。

    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    17.
    发明申请
    SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING 审中-公开

    公开(公告)号：US20190087360A1

    公开(公告)日：2019-03-21

    申请号：US16192509

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B. Noyes

    IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

    CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

    METHODS AND SYSTEMS FOR DATA ANALYSIS IN A STATE MACHINE
    18.
    发明申请
    METHODS AND SYSTEMS FOR DATA ANALYSIS IN A STATE MACHINE 有权

    公开(公告)号：US20160379114A1

    公开(公告)日：2016-12-29

    申请号：US15262958

    申请日：2016-09-12

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B. Noyes

    IPC: G06N3/08 ,  G06N3/063

    CPC classification number: G06N3/08 ,  G06K9/00986 ,  G06N3/063

    Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

    METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE
    19.
    发明申请
    METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE 有权
    用于提供状态机发动机接收的数据的方法和装置

    公开(公告)号：US20160371215A1

    公开(公告)日：2016-12-22

    申请号：US15257677

    申请日：2016-09-06

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit S. Bains

    IPC: G06F13/40

    CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

    Abstract translation: 装置可以包括被配置为从处理器接收数据流的第一部分的第一状态机引擎和被配置为从处理器接收数据流的第二部分的第二状态机引擎。 该装置包括缓冲器接口，该缓冲器接口被配置为使能第一和第二状态机引擎之间的数据传输。 缓冲器接口包括耦合到第一和第二状态机引擎的接口数据总线。 缓冲器接口被配置为在第一和第二状态机引擎之间提供数据。

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