公开(公告)号：US09275698B2

公开(公告)日：2016-03-01

申请号：US14339680

申请日：2014-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Paul A. LaBerge ,  Joseph M. Jeddeloh ,  James B. Johnson

IPC: G06F13/00 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4096 ,  G11C29/02 ,  G06F12/00 ,  G11C7/22 ,  G11C11/401

CPC classification number: G11C7/1072 ,  G06F12/00 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/107

Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

公开(公告)号：US20140040696A1

公开(公告)日：2014-02-06

申请号：US14046785

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： James B. Johnson

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1008 ,  H03M13/05 ,  H03M13/09 ,  H04L1/0052 ,  H04L1/0057

Abstract: Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.

Abstract translation: 已经提出纠错码（ECC）用于高频存储器件中以检测在存储器控制器和存储器件之间传输的信号中的错误。 对于高频存储器件，ECC具有大于1个时钟周期的延迟特性。 当延迟超过一个时钟周期但远小于两个时钟周期时，必须添加整个第二个时钟周期。 通过计算和比较静态逻辑电路中的ECC值和动态逻辑电路，逻辑延迟显着降低。 此外，可以使用两组静态逻辑门来计算和比较ECC值，其中第二静态逻辑门由相对于第一组逻辑门的时钟信号延迟的时钟信号计时。

公开(公告)号：US20130318298A1

公开(公告)日：2013-11-28

申请号：US13956045

申请日：2013-07-31

Applicant: Micron Technology, Inc.

Inventor： Paul A. LaBerge ,  James B. Johnson

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0673 ,  G06F3/0689 ,  G06F5/06 ,  G06F13/1689 ,  G06F2003/0697 ,  G11C7/1051 ,  G11C7/222 ,  Y02D10/14

Abstract: Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.