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    SIGNAL ROUTING STRUCTURES INCLUDING A PLURALITY OF PARALLEL CONDUCTIVE LINES AND SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING THE SAME
    1.
    发明公开
    SIGNAL ROUTING STRUCTURES INCLUDING A PLURALITY OF PARALLEL CONDUCTIVE LINES AND SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230268351A1

    公开(公告)日：2023-08-24

    申请号：US18096458

    申请日：2023-01-12

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh ,  James B. Johnson

    IPC: H01L27/12

    CPC classification number: H01L27/124

    Abstract: A semiconductor device assembly includes a first semiconductor device having a first plurality of electrical contacts with a first average pitch, a second semiconductor device over the first semiconductor device and having a second plurality of electrical contacts with a second average pitch, and a signal routing structure between the first and second semiconductor devices and including a first plurality of conductive structures, each in contact with one of the first plurality of electrical contacts, a second plurality of conductive structures, each in contact with one of the second plurality of electrical contacts, and a pattern of parallel conductive lines between the first and second pluralities of conductive structures. The pattern of parallel conductive lines has a third average pitch less than the first and second average pitches, and pairs of conductive structures from the first and second pluralities are electrically coupled by different ones of the parallel conductive lines.

    PROCESSING IN MEMORY REGISTERS
    3.
    发明申请
    PROCESSING IN MEMORY REGISTERS 有权

    公开(公告)号：US20250069629A1

    公开(公告)日：2025-02-27

    申请号：US18786480

    申请日：2024-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Dmitri Yudanov ,  James B. Johnson ,  Peter L. Brown ,  Glen E. Hush

    IPC: G11C7/10 ,  G11C7/08 ,  G11C7/22

    Abstract: Processing can occur in registers of a memory sub-system. A first plurality of registers coupled to the plurality of sense amplifiers can store the first plurality of bits received from the plurality of sense amplifiers. Processing circuitry coupled to the first plurality of registers can receive the first plurality of bits from the first plurality of registers and can perform an operation on the first plurality of bits to generate result bits. A second plurality of registers coupled to the processing circuitry and the plurality of registers can store the result bits received from the processing circuitry and can provide the result bits to a plurality of data input/output (I/O) lines prior to storing a second plurality of bits.

    Self-timed error correcting code evaluation system and method
    4.
    发明授权
    Self-timed error correcting code evaluation system and method 有权
    自定义纠错码评估系统及方法

    公开(公告)号：US08930786B2

    公开(公告)日：2015-01-06

    申请号：US14046785

    申请日：2013-10-04

    Applicant: Micron Technology, Inc

    Inventor： James B. Johnson

    IPC: H04L1/14 ,  G06F11/10 ,  H03M13/09 ,  H04L1/00 ,  H03M13/05

    CPC classification number: G06F11/10 ,  G06F11/1008 ,  H03M13/05 ,  H03M13/09 ,  H04L1/0052 ,  H04L1/0057

    Abstract: Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.

    Abstract translation: 已经提出纠错码（ECC）用于高频存储器件中以检测在存储器控制器和存储器件之间传输的信号中的错误。 对于高频存储器件，ECC具有大于1个时钟周期的延迟特性。 当延迟超过一个时钟周期但远小于两个时钟周期时，必须添加整个第二个时钟周期。 通过计算和比较静态逻辑电路中的ECC值和动态逻辑电路，逻辑延迟显着降低。 此外，可以使用两组静态逻辑门来计算和比较ECC值，其中第二静态逻辑门由相对于第一组逻辑门的时钟信号延迟的时钟信号计时。

    Memory system and method using stacked memory device dice, and system using the memory system
    6.
    发明授权
    Memory system and method using stacked memory device dice, and system using the memory system 有权
    内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统

    公开(公告)号：US08793460B2

    公开(公告)日：2014-07-29

    申请号：US14010159

    申请日：2013-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Paul A. LaBerge ,  Joseph M. Jeddeloh ,  James B. Johnson

    IPC: G06F13/00

    CPC classification number: G11C7/1072 ,  G06F12/00 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/107

    Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

    Abstract translation: 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。

    Self-timed error correcting code evaluation system and method
    7.
    发明授权
    Self-timed error correcting code evaluation system and method 有权

    公开(公告)号：US08555127B2

    公开(公告)日：2013-10-08

    申请号：US13731658

    申请日：2012-12-31

    Applicant: Micron Technology, Inc.

    Inventor： James B. Johnson

    IPC: H04L1/14 ,  H03M13/00 ,  G11C29/00

    CPC classification number: G06F11/10 ,  G06F11/1008 ,  H03M13/05 ,  H03M13/09 ,  H04L1/0052 ,  H04L1/0057

    Abstract: Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.

    SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD
    8.
    发明申请
    SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD 有权

    公开(公告)号：US20130117628A1

    公开(公告)日：2013-05-09

    申请号：US13731658

    申请日：2012-12-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： James B. Johnson

    IPC: H03M13/05

    CPC classification number: G06F11/10 ,  G06F11/1008 ,  H03M13/05 ,  H03M13/09 ,  H04L1/0052 ,  H04L1/0057

    Abstract: Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.

    MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM
    10.
    发明申请
    MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 有权
    使用堆叠存储器设备的存储器系统和方法，以及使用存储器系统的系统

    公开(公告)号：US20130346722A1

    公开(公告)日：2013-12-26

    申请号：US14010159

    申请日：2013-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Paul A. LaBerge ,  Joseph M. Jeddeloh ,  James B. Johnson

    IPC: G06F12/00

    CPC classification number: G11C7/1072 ,  G06F12/00 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/107

    Abstract: A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

    Abstract translation: 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。

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