公开(公告)号：US20230011150A1

公开(公告)日：2023-01-12

申请号：US17933443

申请日：2022-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian Huang ,  Zhenming Zhou ,  Zhongguang Xu ,  Murong Lang

IPC: G06F11/07 ,  G11C16/26 ,  G06F11/10

Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

公开(公告)号：US20220374157A1

公开(公告)日：2022-11-24

申请号：US17323089

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou ,  Zhenlei Shen

IPC: G06F3/06 ,  G06F11/07

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying, by the processing device, a plurality of partitions located on a die of the memory device. The operations performed by the processing device further include selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

公开(公告)号：US11467900B2

公开(公告)日：2022-10-11

申请号：US16928710

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Jian Huang ,  Jiangli Zhu

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/07 ,  G06F3/06 ,  G06F11/30

Abstract: An error associated with a read operation corresponding to a target memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. The first read throughput level is adjusted to a second read throughput level. A read retry operation associated with the target memory die is executed at the second read throughput level.

公开(公告)号：US11449377B2

公开(公告)日：2022-09-20

申请号：US16996267

申请日：2020-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jian Huang ,  Zhenming Zhou ,  Zhongguang Xu ,  Murong Lang

IPC: G06F11/00 ,  G06F11/07 ,  G11C16/26 ,  G06F11/10 ,  G11C16/04

Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

公开(公告)号：US12217794B2

公开(公告)日：2025-02-04

申请号：US18425619

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

公开(公告)号：US11947421B2

公开(公告)日：2024-04-02

申请号：US17958920

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Jian Huang ,  Jiangli Zhu

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/30

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1471 ,  G06F11/3037

Abstract: An error associated with a read operation corresponding to a memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. A quantity of queues receiving operation requests is decreased, the decreased quantity of queues corresponding to a second read throughput level. A read retry operation associated with the memory die is initiated at the second read throughput level.

公开(公告)号：US20230207028A1

公开(公告)日：2023-06-29

申请号：US17580105

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou ,  Murong Lang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26

Abstract: A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block.

公开(公告)号：US20230186995A1

公开(公告)日：2023-06-15

申请号：US17546425

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C29/4401 ,  G11C2029/1202

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits set satisfies a threshold criterion, copying second data from the first block to a second block.

公开(公告)号：US20230069559A1

公开(公告)日：2023-03-02

申请号：US17462605

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

公开(公告)号：US20220137854A1

公开(公告)日：2022-05-05

申请号：US17088280

申请日：2020-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Murong Lang ,  Jian Huang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G06F3/06

Abstract: An operation timing condition associated with a memory device to be installed at a memory sub-system is determined. The memory device can include a cross-point array of non-volatile memory cells. The operation timing condition corresponds to a first operation delay timing margin setting for the cross-point array of non-volatile memory cells. A first set of memory access operations is performed at the cross-point array of non-volatile memory cells according to a second operation delay timing margin setting that is lower than the first operation delay timing margin setting. A first number of errors that occurred during performance of the first set of memory access operations is determined. In response to a determination that the first number of errors satisfies an error condition, a first quality rating is assigned for the memory device. In response to a determination that the first number of errors does not satisfy the error criterion, further testing is performed for the cross-point array of non-volatile memory cells based on one or more power level settings.