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公开(公告)号：US20250118364A1
公开(公告)日：2025-04-10
申请号：US18988243
申请日：2024-12-19
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Tingjun Xie , Jiangli Zhu , Nagendra Prasad Ganesh Rao , Sead Zildzic
IPC: G11C11/56
Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.
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公开(公告)号：US12216529B2
公开(公告)日：2025-02-04
申请号：US17933443
申请日：2022-09-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jian Huang , Zhenming Zhou , Zhongguang Xu , Murong Lang
Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
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公开(公告)号：US12062394B2
公开(公告)日：2024-08-13
申请号：US17546425
申请日：2021-12-09
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C29/4401 , G11C2029/1202
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits set satisfies a threshold criterion, copying second data from the first block to a second block.
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公开(公告)号：US11861178B2
公开(公告)日：2024-01-02
申请号：US17462605
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Jian Huang , Tingjun Xie , Murong Lang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.
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公开(公告)号：US11720273B2
公开(公告)日：2023-08-08
申请号：US17323089
申请日：2021-05-18
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou , Zhenlei Shen
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0688 , G06F11/076 , G06F11/0727
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying, by the processing device, a plurality of partitions located on a die of the memory device. The operations performed by the processing device further include selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.
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Patent Agency Ranking
公开(公告)号：US20210012850A1
公开(公告)日：2021-01-14
申请号：US16510778
申请日：2019-07-12
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou
Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.
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公开(公告)号：US20250061928A1
公开(公告)日：2025-02-20
申请号：US18936298
申请日：2024-11-04
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Zhenming Zhou , Jian Huang , Zhongguang Xu , Jiangli Zhu
IPC: G11C7/10
Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_ of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
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公开(公告)号：US20240087655A1
公开(公告)日：2024-03-14
申请号：US17942977
申请日：2022-09-12
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Z. Htet , Sead Zildzic, JR. , Thomas Fiala , Jian Huang , Zhenming Zhou
Abstract: A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.
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公开(公告)号：US20230395176A1
公开(公告)日：2023-12-07
申请号：US18205083
申请日：2023-06-02
Applicant: Micron Technology, Inc.
Inventor： Jian Huang , Zhenming Zhou
CPC classification number: G11C29/32 , G11C29/1201
Abstract: A method includes determining, for a plurality of memory dice, binning information relating to quality characteristics of each of the plurality of memory dice. The method further includes performing a select gate scan to determine a first threshold voltage and a first threshold voltage window of each of the plurality of memory dice, and, based on the determined quality characteristics of each of the plurality of memory dice, perform an erase and program operation to set a second threshold voltage with a second threshold voltage window of a subset of memory dice among the plurality of memory dice where the second threshold voltage window is greater than the first threshold voltage window.
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公开(公告)号：US20230393752A1
公开(公告)日：2023-12-07
申请号：US17887244
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Nagendra Prasad Ganesh Rao , Joshua C. Garrison , Jian Huang
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679 , G11C16/34 , G11C16/0483
Abstract: An example system can include a memory component and a processing device. The memory component can include a group of memory cells. The processing device can be coupled to the memory component. The processing device can be configured to use a first voltage window for a set of memory cells of the group of memory cells during a first time period. The processing device can be configured to determine that an error rate of a sub-set of the set of memory cells is above a threshold error rate. The processing device can be configured to, in response to the determination that the error rate of the sub-set of memory cells is above the threshold error rate, use a second voltage window for the set of memory cells of the group of memory cells during a second time period.
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