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公开(公告)号:US12272418B2
公开(公告)日:2025-04-08
申请号:US18242884
申请日:2023-09-06
Applicant: Micron Technology, Inc.
Inventor: Zhongguang Xu , Zhenlei Shen , Murong Lang
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.
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公开(公告)号:US20250061928A1
公开(公告)日:2025-02-20
申请号:US18936298
申请日:2024-11-04
Applicant: Micron Technology, Inc.
Inventor: Murong Lang , Zhenming Zhou , Jian Huang , Zhongguang Xu , Jiangli Zhu
IPC: G11C7/10
Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_ of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
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公开(公告)号:US12182433B2
公开(公告)日:2024-12-31
申请号:US17892581
申请日:2022-08-22
Applicant: Micron Technology, Inc.
Inventor: Zhongguang Xu
IPC: G06F3/06
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.
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公开(公告)号:US20240145010A1
公开(公告)日:2024-05-02
申请号:US18404827
申请日:2024-01-04
Applicant: Micron Technology, Inc.
Inventor: Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号:US20230011150A1
公开(公告)日:2023-01-12
申请号:US17933443
申请日:2022-09-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Jian Huang , Zhenming Zhou , Zhongguang Xu , Murong Lang
Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
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公开(公告)号:US11449377B2
公开(公告)日:2022-09-20
申请号:US16996267
申请日:2020-08-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Jian Huang , Zhenming Zhou , Zhongguang Xu , Murong Lang
Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
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公开(公告)号:US20250140325A1
公开(公告)日:2025-05-01
申请号:US18784315
申请日:2024-07-25
Applicant: Micron Technology, Inc.
Inventor: Hanping Chen , Zhongguang Xu
Abstract: Apparatuses and methods for performing read operations on partially programmed blocks are provided. One example apparatus can include a controller configured to apply a read voltage to the first inner word line in the array of memory cells during a read operation on the first inner word line, apply a first pass voltage to a second inner word line adjacent to the first inner word line and to a third inner word line adjacent to the first inner word line, apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells in response to determining the read request is for data stored on the first inner word line of the partially programmed block, and apply a third pass voltage to a first number of inner word lines of the number of word lines that are nonadjacent to the first inner word line.
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公开(公告)号:US12260916B2
公开(公告)日:2025-03-25
申请号:US18404827
申请日:2024-01-04
Applicant: Micron Technology, Inc.
Inventor: Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号:US12216529B2
公开(公告)日:2025-02-04
申请号:US17933443
申请日:2022-09-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Jian Huang , Zhenming Zhou , Zhongguang Xu , Murong Lang
Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.
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公开(公告)号:US20240331784A1
公开(公告)日:2024-10-03
申请号:US18619094
申请日:2024-03-27
Applicant: Micron Technology, Inc.
Inventor: Hanping Chen , Zhongguang Xu , Christina Papagianni , Yu-Chung Lien , Zhenming Zhou
CPC classification number: G11C16/3459 , G11C16/102 , G11C29/52
Abstract: A defective portion of a block of a memory device is identified. The defective portion of the block is programmed with a pre-programming voltage pattern. The pre-programming voltage pattern is programmed to the defective portion of the block before a programming operation is performed on a non-defective portion of the block. A verification operation is caused to be performed on the defective portion of the block.
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