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    OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD
    2.
    发明申请
    OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD 有权

    公开(公告)号：US20250061928A1

    公开(公告)日：2025-02-20

    申请号：US18936298

    申请日：2024-11-04

    Applicant: Micron Technology, Inc.

    Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

    IPC: G11C7/10

    Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_ of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.

    Adaptive memory partition closure time
    3.
    发明授权
    Adaptive memory partition closure time 有权

    公开(公告)号：US12182433B2

    公开(公告)日：2024-12-31

    申请号：US17892581

    申请日：2022-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu

    IPC: G06F3/06

    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.

    ADAPTIVE FREQUENCY CONTROL FOR HIGH-SPEED MEMORY DEVICES
    5.
    发明申请
    ADAPTIVE FREQUENCY CONTROL FOR HIGH-SPEED MEMORY DEVICES 有权

    公开(公告)号：US20230011150A1

    公开(公告)日：2023-01-12

    申请号：US17933443

    申请日：2022-09-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jian Huang ,  Zhenming Zhou ,  Zhongguang Xu ,  Murong Lang

    IPC: G06F11/07 ,  G11C16/26 ,  G06F11/10

    Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

    Adaptive frequency control for high-speed memory devices
    6.
    发明授权
    Adaptive frequency control for high-speed memory devices 有权

    公开(公告)号：US11449377B2

    公开(公告)日：2022-09-20

    申请号：US16996267

    申请日：2020-08-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jian Huang ,  Zhenming Zhou ,  Zhongguang Xu ,  Murong Lang

    IPC: G06F11/00 ,  G06F11/07 ,  G11C16/26 ,  G06F11/10 ,  G11C16/04

    Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

    OPERATIONS ON PARTIALLY PROGRAMMED BLOCKS
    7.
    发明申请
    OPERATIONS ON PARTIALLY PROGRAMMED BLOCKS 有权

    公开(公告)号：US20250140325A1

    公开(公告)日：2025-05-01

    申请号：US18784315

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Hanping Chen ,  Zhongguang Xu

    IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

    Abstract: Apparatuses and methods for performing read operations on partially programmed blocks are provided. One example apparatus can include a controller configured to apply a read voltage to the first inner word line in the array of memory cells during a read operation on the first inner word line, apply a first pass voltage to a second inner word line adjacent to the first inner word line and to a third inner word line adjacent to the first inner word line, apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells in response to determining the read request is for data stored on the first inner word line of the partially programmed block, and apply a third pass voltage to a first number of inner word lines of the number of word lines that are nonadjacent to the first inner word line.

    Adaptive frequency control for high-speed memory devices
    9.
    发明授权
    Adaptive frequency control for high-speed memory devices 有权

    公开(公告)号：US12216529B2

    公开(公告)日：2025-02-04

    申请号：US17933443

    申请日：2022-09-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jian Huang ,  Zhenming Zhou ,  Zhongguang Xu ,  Murong Lang

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G11C16/26 ,  G11C16/04

    Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

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