公开(公告)号：US12210752B2

公开(公告)日：2025-01-28

申请号：US18372998

申请日：2023-09-26

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.

公开(公告)号：US12176060B2

公开(公告)日：2024-12-24

申请号：US18531003

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.

公开(公告)号：US12169646B2

公开(公告)日：2024-12-17

申请号：US17716689

申请日：2022-04-08

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22

Abstract: A data structure including a target read voltage level corresponding to each set of values of a plurality of sets of values corresponding to a plurality of operating characteristics is stored. In response to a read command associated with a memory cell, a current set of measured values of the plurality of operating characteristics associated with the memory cell is measured. A match between a first set of values of the plurality of sets of values corresponding to the plurality of operating characteristics and the current set of measured values is identified. Using the data structure, a first stored target read voltage level corresponding to the match between the first set of values and the current set of measured values is identified. The read command is executed using the first stored target read voltage level.

公开(公告)号：US20240312526A1

公开(公告)日：2024-09-19

申请号：US18670073

申请日：2024-05-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3404

Abstract: A processing device in a memory sub-system logically closes a block of a memory device to prevent additional program operations from being performed on the block. The processing device further causes one or more wordlines of the block to be programmed with padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was logically closed. In addition, the processing device causes a remaining set of wordlines of the block to be concurrently programmed to a single program state.

公开(公告)号：US12051471B2

公开(公告)日：2024-07-30

申请号：US17871689

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang ,  Li-Te Chang

IPC: G11C16/34 ,  G11C11/406

CPC classification number: G11C16/3418 ,  G11C11/40618 ,  G11C16/349

Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

公开(公告)号：US20240231666A1

公开(公告)日：2024-07-11

申请号：US18617430

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Peng Zhang ,  Murong Lang ,  Christina Papagianni ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.

公开(公告)号：US12013792B2

公开(公告)日：2024-06-18

申请号：US17842278

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/10 ,  G06F12/06 ,  G06F12/1027 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F12/1027 ,  G06F12/0692 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G06F2212/68 ,  G11C16/0483

Abstract: A read command is received by a processing device coupled to a memory device. The read command specified a logical address. The processing device translates the logical address into a physical address of a physical block of the memory device, wherein the physical address specifies a wordline and a memory device die. Responsive to determining that the physical block is partially programmed, the processing device identifies a threshold voltage offset associated with the wordline. The processing device computes a modified threshold voltage by applying the threshold voltage offset to a read level associated with the memory device die. The processing device reads the data from the physical block using the modified threshold voltage.

公开(公告)号：US20240177795A1

公开(公告)日：2024-05-30

申请号：US18519248

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Aaron Lee ,  Zhenming Zhou ,  Murong Lang

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

Abstract: A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

公开(公告)号：US11960745B2

公开(公告)日：2024-04-16

申请号：US17889757

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Peng Zhang ,  Murong Lang ,  Christina Papagianni ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.

公开(公告)号：US20240105240A1

公开(公告)日：2024-03-28

申请号：US18531003

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

CPC classification number: G11C7/1063

Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.