公开(公告)号：US11581032B2

公开(公告)日：2023-02-14

申请号：US17235775

申请日：2021-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki

IPC: G11C5/14 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4074 ,  G11C7/06

Abstract: An apparatus including a temperature dependent circuit is configured to receive a temperature dependent power supply voltage, and further is configured to receive a first input signal and provide a temperature dependent output signal responsive to the input signal. A power control circuit including the temperature dependent circuit is configured to receive a second input signal, and further configured provide a first control voltage based on the first temperature dependent output signal and provide a second control voltage based on the second input signal. The second control voltage has a temperature dependency based on the temperature dependent power supply voltage. A sense amplifier coupled to a pair of digit lines is configured to receive the first and second control voltages and amplify a voltage difference between the digit lines of the pair.

公开(公告)号：US10373655B2

公开(公告)日：2019-08-06

申请号：US15833643

申请日：2017-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada ,  Sachiko Edo

IPC: G11C5/14 ,  G05F3/24

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.

公开(公告)号：US20190172505A1

公开(公告)日：2019-06-06

申请号：US15833643

申请日：2017-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada ,  Sachiko Edo

IPC: G11C5/14 ,  G05F3/24

CPC classification number: G11C5/147 ,  G05F3/24 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/46 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.

公开(公告)号：US12277986B2

公开(公告)日：2025-04-15

申请号：US17475206

申请日：2021-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki

IPC: G11C29/50 ,  G11C11/408

Abstract: Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage are described. An example apparatus includes a first subword line and a second subword line coupled to the first subword line by a first common transistor where, in response to a test mode signal, a voltage of each of the first and second subword lines is raised to a first voltage and a gate voltage of the first common transistor is raised to a second voltage. In another example apparatus first and second subword drivers are coupled to the first and second subword lines respectively, and a driver circuit is coupled to the first and second subword drivers. The driver circuit outputs a first high signal to cause the first and second subword lines to rise to the first voltage and the gate voltage of the first common transistor to rise to the second voltage.

公开(公告)号：US20240355378A1

公开(公告)日：2024-10-24

申请号：US18758749

申请日：2024-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4093 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

公开(公告)号：US20230019887A1

公开(公告)日：2023-01-19

申请号：US17936166

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4093 ,  G11C11/4076

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

公开(公告)号：US11475939B2

公开(公告)日：2022-10-18

申请号：US17125095

申请日：2020-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G01R31/26 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

公开(公告)号：US20220199146A1

公开(公告)日：2022-06-23

申请号：US17125095

申请日：2020-12-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4093

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

公开(公告)号：US10559343B1

公开(公告)日：2020-02-11

申请号：US16508162

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4076 ,  G11C11/4093

Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.

公开(公告)号：US20200027494A1

公开(公告)日：2020-01-23

申请号：US16508162

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4076 ,  G11C11/4093

Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.