公开(公告)号：US20230360681A1

公开(公告)日：2023-11-09

申请号：US17740069

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C7/10 ,  G11C16/34

CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1066 ,  G11C16/3404

Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

公开(公告)号：US11062767B2

公开(公告)日：2021-07-13

申请号：US16733152

申请日：2020-01-02

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C11/54 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  G06N3/04

Abstract: Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

公开(公告)号：US20210104276A1

公开(公告)日：2021-04-08

申请号：US17104547

申请日：2020-11-25

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C13/00 ,  G11C11/54 ,  G06N3/08 ,  G06N3/063

Abstract: In an example, an apparatus can include an array of memory cells and a neural memory unit controller coupled to the array of memory cells and configured to assert respective voltage pulses during a first training interval to memory cells of the array to change respective threshold voltages of the memory cells from voltages associated with a reset state to effectuate respective synaptic weight changes. The neural memory unit controller can be configured to initiate a sleep interval, during which no pulses are applied to the memory cells, to effectuate respective voltage drifts in the changed respective threshold voltages of the memory cells from a voltage associated with a set state toward the voltage associated with the reset state, and determine an output of the memory cells responsive to the respective voltage drifts in the changed respective threshold voltages after the sleep interval.

公开(公告)号：US10861539B1

公开(公告)日：2020-12-08

申请号：US16546520

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C11/54 ,  G06N3/08 ,  G06N3/063 ,  G11C13/00 ,  H01L45/00

Abstract: In an example, an apparatus can include an array of memory cells and a neural memory unit controller coupled to the array of memory cells and configured to assert respective voltage pulses during a first training interval to memory cells of the array to change respective threshold voltages of the memory cells from voltages associated with a reset state to effectuate respective synaptic weight changes. The neural memory unit controller can be configured to initiate a sleep interval, during which no pulses are applied to the memory cells, to effectuate respective voltage drifts in the changed respective threshold voltages of the memory cells from a voltage associated with a set state toward the voltage associated with the reset state, and determine an output of the memory cells responsive to the respective voltage drifts in the changed respective threshold voltages after the sleep interval.

公开(公告)号：US10553792B2

公开(公告)日：2020-02-04

申请号：US15841356

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Mattia Boniardi ,  Enrico Varesi ,  Raffaella Calarco ,  Jos E. Boschker

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.

公开(公告)号：US20190378566A1

公开(公告)日：2019-12-12

申请号：US16001790

申请日：2018-06-06

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G11C11/54 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00

Abstract: Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

公开(公告)号：US10008668B2

公开(公告)日：2018-06-26

申请号：US15607095

申请日：2017-05-26

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Andrea Redaelli

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2427 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.

公开(公告)号：US09614007B2

公开(公告)日：2017-04-04

申请号：US14803303

申请日：2015-07-20

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Andrea Redaelli

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.

公开(公告)号：US09461246B2

公开(公告)日：2016-10-04

申请号：US15064002

申请日：2016-03-08

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Andrea Redaelli

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

公开(公告)号：US09312481B2

公开(公告)日：2016-04-12

申请号：US14226643

申请日：2014-03-26

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Andrea Redaelli

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

Abstract translation: 一些实施例包括在位线和字线之间垂直地具有多个存储单元的存储器阵列。 存储单元包含相变材料。 热屏蔽沿着位线方向横向位于紧邻的存储单元之间。 隔热罩包含导电材料并与位线电连接。 一些实施例包括具有布置在第一网格中的多个存储单元的存储器阵列。 第一格栅具有沿着第一方向的列，并且沿着与第一方向大致正交的第二方向具有列。 第一热屏蔽沿着第一方向位于相邻存储单元之间，并且沿着第一方向布置成与第一格栅偏移的第二格栅。 第二隔热板沿着第二方向位于相邻存储单元之间，并沿着第一方向延伸的线排列。 一些实施例包括用于形成存储器阵列的方法。